DØ Run. IIb Trigger Upgrade: Status and Review Response Darien Wood for the DØ Trigger Upgrade Group 1
The Run IIb Trigger System Detector CAL Level 1 7 MHz 2. 5 k. Hz L 1 Cal Level 2 1 k. Hz L 2 Cal Cal-TRK c/f PS L 1 PS L 2 PS CFT L 1 CTT L 2 CTT SMT L 2 STT L 1 Mu MU FPD MU-TRK L 2 Mu L 1 FPD Lumi Framework New (or replaced) System 50 Hz Enhanced System 2 Global L 2 L 3/DAQ Level 3 D 0 PMG 07 -Sep-2004
Upgrade L 1 Cal: Major features · Calorimeter trigger upgrade u sharpens turn-on trigger thresholds u more topological cuts · Largest subproject in the trigger upgrade · Will require removing the existing Cal trigger 3 D 0 PMG 07 -Sep-2004
L 1 Cal. Track: Major features · Exploit new L 1 Cal trigger · Improve Run IIa f matching granularity x 8 · Needed in triggers for Higgs searches u u electrons in WH and H W*W modes taus in H tt and H+ t · Fake EM rejection is improved by ~x 2 · Fake t rejection is improved by ~x 10 · Very modest upgrade modeled on existing Mu -Track match system u 4 Very few changes with respect to Mu-Track D 0 PMG 07 -Sep-2004
Upgrade L 1 CTT: Major features · Level 1 Central Track Trigger (CTT) essential for electrons, muons, taus (WH l jj) · Tracking trigger rates sensitive to occupancy · Upgrade stategy: u Narrow tracker roads by using individual fiber hits (singlets) rather than pairing adjacent fibers (doublets) u Cal-track matching 5 D 0 PMG 07 -Sep-2004
Scope of Upgrade L 1 CTT · Original idea was to simply replace FPGAs to newer larger ones that allow more equations · Have recently upscoped the project to allow monitoring and debugging capability · The project now involves replacing two crates of electronics and the crates themselves · All elements in this upgrade have been designed to minimize commissioning time and simplify debugging 6 D 0 PMG 07 -Sep-2004
Upgrade Level 2: Major features · Level 2 STT – simply buy more boards to include the new layer 0 · Level 2 Processors. Just buy new faster processors to allow more functionality at this trigger level 7 D 0 PMG 07 -Sep-2004
Management structure WBS 1. 2: Trigger Upgrade P. Padley (Rice), D. Wood (Northeastern) Project is largely university based WBS 1. 2. 1: Level 1 Calorimeter M. Abolins(MSU), H. Evans(Columbia) WBS 1. 2. 2: Level 1 Cal-track match K. Johns (Arizona) WBS 1. 2. 3: Level 1 Tracking M. Narain (Boston), Don Lincoln (FNAL) WBS 1. 2. 4: Level 2 Beta upgrade R. Hirosky (Virginia) WBS 1. 2. 5: Level 2 STT upgrade U. Heintz (Boston) WBS 1. 2. 6: Trigger Simulation M. Hildreth (ND), E. Barberis (NEU) WBS 1. 2. 7: AFE upgrade (Pending) A. Bross (FNAL) 8 D 0 PMG 07 -Sep-2004
WBS 1. 2. 1: L 1 Cal ADC+digital filtering Clustering Global sums & topological 9 D 0 PMG 07 -Sep-2004
L 1 Cal progress since July 16 · ADF v. 2 design complete; estimate completion of layout in ~2 weeks u u thorough attention by lead engineer (Dan Edmunds) to details of design and layout visit by Marvin Johnson to MSU in August s s review of design consulting on noise immunity issues · SCLD: benchtest completed on final module 10 D 0 PMG 07 -Sep-2004
ADF v. 2 Layout · Traces u u u 4279 completed 428 in progress 1052 remaining (all digital) · Channel link section took longer than anticipated 11 D 0 PMG 07 -Sep-2004
SCLD (Distributes SCL for the ADF system) u u A prototype has been used successfully in integration tests. Final (multichannel) board has successfully passed bench tests at Saclay Final Multichannel SCLD 12 D 0 PMG 07 -Sep-2004
BLS to ADF cables and staging area · UIC and Fermilab completed design & layout of transition elements in August u u Pleated foil cables Paddle transition card · New racks set up in sidewalk area at end of August 13 D 0 PMG 07 -Sep-2004
TAB and GAB · Additional small board designed at Nevis to test GAB communication with Trigger Framework · Orders placed for all remaining TAB and GAB components · Production readiness review for TAB in Sep/Oct · Continued progress on firmware and test software 14 D 0 PMG 07 -Sep-2004
L 1 Cal. Track Trigger Overview 15 D 0 PMG 07 -Sep-2004
Cal-track progress since July 16 · Production MTCM fabricated and assembled · MTT – MTCxx/UFB – MTCM – MTT loop test established u u Serial inputs from test card Simple trigger algorithm on MTCxx/UFB Trigger output to test card via crate manager Compare hardware and expected result · Resistive load built to test L 1 Cal. Track and L 1 MU supplies (thank you Valerie Tokemenin) · Prep work for collision hall cable termination 16 D 0 PMG 07 -Sep-2004
Production MTCM 17 D 0 PMG 07 -Sep-2004
Level 1 Central Track Trigger progress since July 16 (1) · Combined DFEA motherboard-daughterboard u u 5 PCB’s fabricated 2 boards stuffed (rec’d Aug 4 th) still missing 48 V converters – work around for now Passed power-up and JTAG programming tests · DFEA stand alone tester u u u Two boards received back from assembler Used in some preliminary tests of DFEA’s Firmware & software mostly done s 18 Remaining: commission SLDB receiver D 0 PMG 07 -Sep-2004
DFEA pre-prod (w/ integrated motherboard) 19 D 0 PMG 07 -Sep-2004
DFEA stand-alone tester 20 D 0 PMG 07 -Sep-2004
Level 1 Central Track Trigger progress since July 16 (2) · New DFE crate backplane u u u PCB’s finished end of July connectors installed by Bustronics in August Received at Fermilab 11 Aug Alignment looks good Further testing once power supplies are received (shipped last week) · LVDS splitters u u u 21 assembly finished end of August Test completed Installed on platform D 0 PMG 07 -Sep-2004
Level 1 Central Track Trigger progress since July 16 (3) · New DFE crate controllers u u Two PCB’s arrived 11 August Stuffed by Bob Jones’ technicians No major problems found Firmware development s s s u 22 Ethernet interface: 100% Backplane interface: 95% (testing) SCL receiver: 75% (testing) Communicating with Linux host PC with no problems D 0 PMG 07 -Sep-2004
L 1 CTT parallel chain Mixer LVDS splitters DFEA crates CTOC, etc (current) Extra CTOC, CTTT Fiber signals Trigger framework timing (Serial command link) Partial Prototype crate prototype DFEA controller crate (upgrade) Parallel slice of upgrade prototypes to be installed in Aug 04 shutdown 23 link PC D 0 PMG 07 -Sep-2004
L 1 CTT: 04 Shutdown progress · Completed: u Installed two LVDS splitters between mixer and DFEA s System checked OK Will split 4 sectors s ODH safety hardware will have to be moved s u u u LVDS cables checked: OK SCL cables confirmed to be working Space check in PWO 2 for upgrade DFEA crate · Still to do u u u Install upgrade DFEA crate on platform (PW 02) (~3 days) Install and cable additional CTOC and CTTT (~3 days) Verify current system is unaffected by modifications (~1 w) · Installation of new DFEA prototypes and new Crate Controller can occur on short accesses (~2 hrs) if necessary once above work is completed 24 D 0 PMG 07 -Sep-2004
L 2 Beta Upgrade progress since July 16 · Work in July/August to get the Concurrent Tech c. PCI CPU to work with the 9 u motherboard · mapped out all signals on c. PCI connectors · Surveying market for fallback CPUs in case compatibility issues are not resolved (connections on both main board & mezzanine) · Algorithm development at UVA: coarse vertexing 25 Concurrent Technology P 220 Dual P 4 2 GHz Hyperthreading D 0 PMG 07 -Sep-2004
STT upgrade · This upgrade is simply making more of the boards that are currently used to allow for the inclusion of layer 0 · Production Readiness Review this Friday (10 Sept) in Boston, chaired by Jim Linnemann 26 D 0 PMG 07 -Sep-2004
Simulation: progress since July 16 th · L 1 cal u u u variety of small variations of sliding window algorithm studies for EM triggers optimization point similar to current L 2 EM algorithm “trigger rate tool” adapted to implement sliding windows algorithms s s uses real collider data as input accounts for correlations and combined rates of full trigger list · L 1 CTT u Run IIa simulation package being restructured s 27 will be much more easily adapted to Run IIb D 0 PMG 07 -Sep-2004
Recommendations from July Director’s Review · “Secure the manpower for all installation needs in the 2004 shutdown to allow testing during the data taking in FY 05” u Additional engineering & technical help obtained for CTT. Shutdown progressing well. · “Establish a forum (presumably through the Director for Research) for ongoing dialog with CDF and the AD on the timing of the FY 05 shutdown” u 28 . . . D 0 PMG 07 -Sep-2004
Recommendations from July Director’s Review (cont. ) · “It would be helpful to have a presentation on trigger simulation and validation efforts some time in early 2005” u u Agreed. Some progress will be reported to the collaboration at the Sept. collaboration meeting Simulations for AFE II are a priority right now · “It would be useful to have a presentation of SC-IPC task list around the same time” u 29 Agreed. Draft first report of SC-IPC released to the collaboration in late August D 0 PMG 07 -Sep-2004
Triggers Summary · L 1 cal u u Main focus is ADF v. 2 layout Progress in BLS cable transition · L 1 caltrack u MTCM production finished Installation work in progress in collision hall u New boards in hand being tested u · L 1 CTT s u · L 2 u u DFEA/M pre-production, DSAT, DFE controller prototype Activity progressing in shutdown for parallel chain Beta hardware tests and algorithm development STT PRR this week · Simulation u Cal algorithm optomization More extensive combined simulations with real data u Recommendations being followed u · Director’s review July 04 30 D 0 PMG 07 -Sep-2004
Backups 31 D 0 PMG 07 -Sep-2004
ADV v. 2 layout · straight lines indicate traces still to be routed · mostly on FPGA’s 32 D 0 PMG 07 -Sep-2004
Preproduction MTCxx with Prototype MTFB UFB 33 SLDB’s D 0 PMG 07 -Sep-2004
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