DØ Calorimeter Electronics Upgrade for Tevatron Run II

DØ Calorimeter Electronics Upgrade for Tevatron Run II DØ Collaboration October 2000 IEEE NUCLEAR SCIENCE SYMPOSIUM and MEDICAL IMAGING CONFERENCE Lyon, France 1 Hervé Lebbolo LPNHE Paris October 15 -20, 2000 DØ Calorimeter Electronics Upgrade 2000 IEEE NSS Lyon, France Oct 2000

Fermilab Accelerator Upgrade · Two new machines at FNAL for Run II: u Main Injector s s u 150 Ge. V conventional proton accelerator Supports luminosity upgrade for the collider, future 120 Ge. V fixed-target program, and neutrino production for NUMI Recycler s s 8 Ge. V permanent magnet (monoenergetic) storage ring permits antiproton recycling from the collider · Tevatron Status and Schedule u DØ and CDF roll in – January 2001 u Run II start – March 2001 u 1. 8 Tev 2 Te. V u Goal: ò L dt = 2 fb-1 by 2003 15 fb-1+ by 2006? u Very first p-pbar collisions seen (August 2000) 2 Hervé Lebbolo LPNHE Paris 2 DØ Calorimeter Electronics Upgrade 2000 IEEE NSS Lyon, France Oct 2000

Run II Parameters % Crossings 40% 3 Run II Bunch Spacing 396 ns 132 ns 30% 20% 10% 0% Hervé Lebbolo LPNHE Paris 0 1 2 3 4 5 6 7 8 9 # of Ints. / Crossing 3 DØ Calorimeter Electronics Upgrade 2000 IEEE NSS Lyon, France Oct 2000

Timing m. Bunch structure gap used to form trigger and sample baselines 3. 56 us Run I 6 x 6 superbunch gap 4. 36 us 2. 64 us 396 ns Run II 36 x 36 this gap is too small to form trigger and sample baseline · Design all the electronics, triggers and DAQ to handle bunch structure with a minimum of 132 ns between bunches and higher luminosity · Maintain detector performance 4 Hervé Lebbolo LPNHE Paris 4 DØ Calorimeter Electronics Upgrade 2000 IEEE NSS Lyon, France Oct 2000

Calorimeter Readout Electronics · Objectives u u Accommodate reduced minimum bunch spacing from 3. 5 s to 396 ns or 132 ns and L~ 2 x 1032 cm-2 s-1 Storage of analog signal for 4 s for L 1 trigger formation Generate trigger signals for calorimeter L 1 trigger Maintain present level of noise performance and pile-up performance · Methods LAr det. u u u 5 preamp L 1+L 2 trigger shaper + BLS analog buffer ADC storage Replace preamplifiers Replace shapers Add analog storage Replace calibration system Replace timing and control system Keep Run I ADCs, crates and most cabling to minimize cost and time Hervé Lebbolo LPNHE Paris 5 DØ Calorimeter Electronics Upgrade 2000 IEEE NSS Lyon, France Oct 2000

Calorimeter Electronics Upgrade new calibrated pulse injection SCA analog storage >4 sec, alternate new low noise preamp & driver Trig. sum Bank 0 BLS Card SCA (48 deep) Detc. Filter/ Shaper Preamp/ Driver SCA (48 deep) x 1 x 8 BLS SCA Output Buffer SCA (48 deep) Bank 1 Replace cables for impedence match · · · 6 Shorter shaping ~400 ns Additional buffering for L 2 & L 3 55 K readout channels Replace signal cables from cryostat to preamps (110 30 for impedance match) Replacement of preamps, shapers, baseline subtraction circuitry (BLS) Addition of analog storage (48 -element deep Switched Capacitor Array (SCA)) New Timing and Control New calibration pulser + current cables Hervé Lebbolo LPNHE Paris 6 DØ Calorimeter Electronics Upgrade 2000 IEEE NSS Lyon, France Oct 2000

Preamplifier similar to Run 1 version except • Dual FET frontend • Compensation for detector capacitance • Faster recovery time New output driver for terminated signal transmission in out preamp driver FET New calorimeter preamp · Hybrid on ceramic · 48 preamps on a motherboard · New low-noise switching power supplies in steel box 2” 7 Hervé Lebbolo LPNHE Paris 7 DØ Calorimeter Electronics Upgrade 2000 IEEE NSS Lyon, France Oct 2000

Preamp Species Preamp species Avg. Detector cap. (n. F) Layer readou t Feedbac k cap (p. F) RC (ns) Total preamp s A 0. 26 -0. 56 EM 1, 2, HAD 5 0 13376 B 1. 1 -1. 5 HAD 5 26 2240 C 1. 8 -2. 6 HAD 5 53 11008 D 3. 4 -4. 6 HAD 5 109 8912 E 0. 36 -0. 44 CC EM 3 10 0 9920 F 0. 72 -1. 04 EC EM 3, 4 10 14 7712 G 1. 3 -1. 7 CC EM 4, EC EM 3, 4 10 32 3232 Ha-Hg 2 - 4 EC EM 3, 4 10 47 -110 896 · 14+1 (ICD) species of preamp ICD I — 22 0 384 · Feedback provide compensation for RC from detector capacitance and cable impedance 55680 · Readout in towers of up to 12 layers u 0: EM 1, 1: EM 2, 2 -5: EM 3, 6: EM 4, 7 -10: FH, 11: CH · 4 towers per preamp motherboard provides trigger tower (EM+ HAD) of Dh x D = 0. 2 x 0. 2 8 Hervé Lebbolo LPNHE Paris 8 DØ Calorimeter Electronics Upgrade 2000 IEEE NSS Lyon, France Oct 2000

BLS Card BLS motherboard v 2. 2 BLS daughterboard L 1 SCAs (2+2) L 2 SCA Array of 48 capacitors to pipeline calorimeter signals ~ 1 inch Output Shapers (12) circuit Trigger pickoff/summers · · · · 9 shaper Use 2 L 1 SCA chips for each x 1/x 8 gain - alternate read/write for each superbunch Readout time ~ 6 s (< length SCA buffer) L 2 SCA buffers readout for transfer to ADC after L 2 trigger decision No dead time for 10 KHz L 1 trigger rate Trigger tower formation (0. 2 x 0. 2) for L 1 Rework existing power supplies New T&C signals to handle SCA requirements and interface to L 1/L 2 trigger system( use FPGAs and FIFOs) Hervé Lebbolo LPNHE Paris 9 DØ Calorimeter Electronics Upgrade 2000 IEEE NSS Lyon, France Oct 2000

SCA write address decoder/control reset input. . x 48. . ref cap ref read address decoder/control DØ Calorimeter Electronics Upgrade ed 10 ag Hervé Lebbolo LPNHE Paris 48 deep ck 10 maintain 15 bit dynamic range 12 channels pa · Designed by LBL, FNAL, SUNY Stony Brook (25 k in system) · Not designed for simultaneous read and write operations 1” · two SCA banks alternate reading and writing · 12 bit dynamic range (1/4000) · low and high gain path for each readout channel (X 8/X 1) u out 2000 IEEE NSS Lyon, France Oct 2000

Preamp signal shape · Preamp output is integral of detector signal u rise time > 430 ns u recovery time 15 s u To minimize the effects of pileup, only use 2/3 of the charge in the detector · Shaped signal sampled every seven RF buckets (132 ns) Detector signal · BLS-Finite time difference is measured u u Signal from preamp amplitude · peak at about 300 ns u return to zero by about 1. 2 s u Sample at 320 ns u Mostly insensitive to 396 ns or 132 ns running After shaper Uses three samples earlier Pile-up 320 ns 0 11 Hervé Lebbolo LPNHE Paris 400 11 DØ Calorimeter Electronics Upgrade 800 1200 ns 2000 IEEE NSS Lyon, France Oct 2000

Noise Contributions · Design for u u u 400 ns shaping lower noise – 2 FET input luminosity of 2 x 1032 cm– 2 s-1 · Re-optimized three contributions u Electronics noise: x 1. 6 s s u Uranium noise: x 2. 3 s u shaping time (2 s 400 ns) (~ t) lower noise preamp (2 FET) (~ 1/ 2) shorter shaping time (~ t) Pile-up noise: x 1. 3 s s luminosity (~ L) shorter shaping times (~ t) ê Comparable noise performance at 1032 with new electronics as with old electronics at 1031 ê Simulations of the W mass “benchmark” confirm that pile-up will not limit our W mass at Run II. 12 Hervé Lebbolo LPNHE Paris 12 DØ Calorimeter Electronics Upgrade 2000 IEEE NSS Lyon, France Oct 2000

Estimates of Noise Contributions n. F Ge. V Cell Capacitance U noise EM 3 layer per cell Ge. V 3. 5 Me. V Electronic noise 13 Hervé Lebbolo LPNHE Paris Total 13 DØ Calorimeter Electronics Upgrade 2000 IEEE NSS Lyon, France Oct 2000

Electronics Calibration Goals · Calibrate electronics to better than 1% u u Measure pedestals due to electronics and Ur noise Determine zero suppression limits Determine gains (x 1, x 8) from pulsed channels Study channel-to-channel response; linearity · Commissioning u u Bad channels Trigger verification Check channel mapping Monitoring tool · Oracle Database for storage · Database used to download pedestals and zero-suppression limits to ADC boards 14 Hervé Lebbolo LPNHE Paris 14 DØ Calorimeter Electronics Upgrade 2000 IEEE NSS Lyon, France Oct 2000

Electronics Calibration System 6 commands (3 x 2) 96 currents PIB Pulser Interface Board: • VME interface • automated calibration procedure switch 2 Fanouts (2 x 3 x 16 switches) Pulser Preamp Box LPNHE-Paris LAL-Orsay Power Supply Trigger Pulser: DC current and command generator: • DC current set by 18 -bit DAC • 96 enable registers • 6 -programmable 8 -bit delays for command signals with 2 ns step size 15 Hervé Lebbolo LPNHE Paris 15 Active Fanout with Switches: pulse shaping and distribution • Open switch when receive command signal DØ Calorimeter Electronics Upgrade 2000 IEEE NSS Lyon, France Oct 2000

Calibration Pulser Response · Linear response for DAC pulse height (0 -65 k) · Fully saturate ADC (at DAC= 90 k) Single channel (ADC vs. DAC) mean Deviation from linearity · · · 16 better than 0. 2% Linearity of calibration and calorimeter electronics better than 0. 2% (for DAC < 65 k) Cross-talk in neighboring channels < 1. 5% Uniformity of pulser modules better than 1% No significant noise added from the calibration system Correction factors need to be determined Hervé Lebbolo LPNHE Paris 16 DØ Calorimeter Electronics Upgrade 2000 IEEE NSS Lyon, France Oct 2000

Pulser Signal Shapes Calorimeter Signal at Preamp Input Calorimeter Signal after Preamp and Shaper 400 ns Calibration Signal at Preamp Input Calibration Signal after Preamp and Shaper Signal reflection 400 ns · Response of calorimeter signal w. r. t. calibration signal <1% at max. signal for variation of different parameters (cable length, Zpreamp, Zcable, …) · No test beam running absolute energy scale will have to be established from the data · Maximum response time for EM and hadronic channels differ due to different preamp types. Use delays and modeling to accommodate these · Correct pulser response for different timings and shape · Use initial “guess” based on Monte-Carlo sampling weights and Spice models of the electronics. 17 Hervé Lebbolo LPNHE Paris 17 DØ Calorimeter Electronics Upgrade 2000 IEEE NSS Lyon, France Oct 2000

Conclusions · Dzero is upgrading its detector u L. Argon calorimeter untouched s Harder machine conditions and new environment (solenoid) – New Calorimeter Electronics – Improved ICD – New Central and Forward Preshower Ø Similar performance with 20 x more data · Run II start in 6 months 18 Hervé Lebbolo LPNHE Paris 18 DØ Calorimeter Electronics Upgrade 2000 IEEE NSS Lyon, France Oct 2000