Designing for 100 MHz 1 Designing for 100 MHz

Designing for 100+ MHz 1 Designing for 100+MHz

1999 Designs Demand. . . w Higher system speed w Higher integration — smaller size, less power, better reliability w Lower cost w Shorter development time w Better product differentiation 2 Designing for 100+MHz

Traditional Multi-Chip Boards w Discrete design components — CPU, memory — bus transceivers, PCI controller, FIFOs — Ethernet controller, Graphics accelerator, MPEG, DSP, etc. — programmable logic as glue and custom function w Advantages: — well-documented sophisticated functions — readily available as IP in silicon 3 Designing for 100+MHz

Multi-Chip Board Problems w Physical size w Power consumption and reliability w PC board signal integrity w Limited flexibility — prevents design modifications and upgrades — prevents product diversification — prevents product customization w Poor product differentiation — standard parts = standard architecture 4 Designing for 100+MHz

FPGA Advantages w Smaller size w Lower power consumption w Better signal integrity — fewer PC-board issues w Enhanced flexibility — easy modifications, upgrades, etc. w Enhanced product differentiation — proprietary architectures 5 Designing for 100+MHz

FPGAs Users Want. . . w System clock rate of 100+ MHz w >100, 000 gates w Efficient design methodologies w Availability of well-documented Cores w Reasonable cost 6 Designing for 100+MHz

The FPGA Solution 4 th Generation FPGA Logic+Memory+Routing Multi-Standard Select I/O Temperature Sensing Delay-Locked Loop for Fast Clock and I/O 3. 3 ns Synchronous Dual-Port SRAM 500 Mbps Select. MAP Configuration 7 Designing for 100+MHz

Now the Challenge. . . Design a 100+ MHz system w Together, we can do it. . . — we’ll supply the ingredients. . . — you use them intelligently w But don’t forget. . . — the clock period is less than 10 ns ! 8 Designing for 100+MHz

Designing for 100+ MHz. w Volts, Amps, and Watts — PCB signal distribution — chip inputs and outputs — power and thermal considerations w Ones and zeros — logic emulation w Bits and bytes — memory hierarchy 9 Designing for 100+MHz

Moore Meets Einstein 2048 1024 Trace Length MHz 512 256 128 64 32 16 8 Clock Frequency Inches per 1/4 Clock Period 4 2 1 ’ 65 ’ 70 ’ 75 ’ 80 ’ 85 ’ 90 Year ’ 95 ’ 00 ’ 05 ’ 10 Speed Doubles Every 5 Years…. . . But the speed of light never changes 10 Designing for 100+MHz

Volts, Amps, and Watts w PCB design issues — capacative loading — transmission lines and termination w Chip inputs and outputs — clock distribution and DLLs — I/O standards w Power and thermal considerations — temperature sensing diode — power supply decoupling w Configuration — new Select. MAP mode 11 Designing for 100+MHz

Capacitive Loading w Capacitance slows outputs and increases power — output delay increase: – ~ 25 ps per p. F of additional loading — output power dissipation increase: – 11 µW per MHz per p. F with 3. 3 -V swing w Sources of capacitance — 10 p. F max for each device pin — 2 p. F per inch for narrow traces ( 0. 8 p. F/cm ) — 130 p. F per inch 2 for copper areas ( 20 p. F/cm 2) w IBIS files provide output impedance details Designing for 100+MHz 12

Transmission Lines w Some traces must be treated as transmission lines to minimize ringing — transmission line if round trip > transition time — lumped-capacitance if round trip < transition time w Signal delay on a PCB: — 140 to 180 ps per inch ( 50 to 70 ps/cm) w Lumped-capacitance trace length: — 3 inches max for a 1 -ns transition time (7. 5 cm) — 6 inches max for a 2 -ns transition time (15 cm) Designing for 100+MHz 13

Terminated Transmission Lines Reflections and ringing Traditional Thevenin termination at the end VCC 100 Ω 50 Ω 100 Ω Dynamic termination at the end is better and saves power Series termination at the source is best single source and destination only! 50 Ω 100 p. F 22 Ω 27 Ω 50 Ω (50 Ω Total) 14 Designing for 100+MHz

On-Chip Clock Distribution Clock Data IOB CLB w Clock distribution introduces delay — larger chips suffer more clock delay 15 Designing for 100+MHz

Clock Delay Problems w Clock delay increases clock-to-output times w Clock delay leads to unacceptable input hold time — set-up time is negative w Additional data delay can eliminate the hold time — set-up time becomes positive IOB Flip-Flop — but tolerance build-up widens the data-valid Clock Delay Data window D Q Required Data Valid (without delay) Clock Distribution Delay Required Data Valid (with delay) 16 Designing for 100+MHz

DLLs Maximize I/O Speed w Clock-to-output time plus set-up time determines the I/O speed and data bandwidth — min clock period = max clock-to-out + max setup w Traditional solution: — use highly buffered, balanced clock trees – needed to reduce internal clock skew – cannot totally eliminate the delay w The Virtex solution: — use a Delay-Locked-Loop ( DLL ) – aligns the internal and external clocks – effectively eliminates the clock-distribution delay Designing for 100+MHz 17

Virtex Has 4 Independent DLLs Clock Error Comparator Data IOB Delay CLB w DLLs adjust clock delay to align internal and external clocks — digital closed-loop control 18 — 25 to 200 -MHz range, 35 -picosecond resolution Designing for 100+MHz

Fast Clock-to-Out With DLL w 160 MHz inter-chip data rate — 16 -m. A LVTTL — IOB register to IOB register Virtex FPGA 0. 5 ns D Q DLL 3. 8 ns 1. 9 ns Clock 19 Designing for 100+MHz

LVTTL Data Rate with DLL 1. 4 ns measured clock-to-output delay Output standard = LVTTL Fast 16 m. A (OBUF_F_16) Temp=100 C, Vdd=2. 375 V, Vcco=3. 3 V Waveforms: 1: CLKIN 2: DATA OUT (no DLL) 3: DATA OUT (DLL deskewed) Timing w/o DLL w/ DLL r->r r->f 3. 9 n 1. 4 n 20 Designing for 100+MHz

Other DLL Functions w Double the incoming clock frequency — fast internal operation – slow external clock w Clock mirroring to the PCB w Divide clock by 1. 5, 2, 2. 5, 3, 4, 5, 8, or 16 w Adjust clock duty cycle to 50 -50 w Create four quadrature clock phases — input four sequential bits per clock period 21 Designing for 100+MHz

Duty Cycle Correction ~25% duty cycle in – 50% duty cycle out Virtex FPGA 1 X 25 MHz 25% Duty Cycle DLL 25 MHz 50% Duty Cycle 22 Designing for 100+MHz

Clock Doubling and Mirroring w Clock mirror with less than 100 ps skew — simplifies PCB clock distribution Virtex System Clock 37 MHz 74 MHz #1 DLL 1 1 Input Load Zero-Delay Internal Clock Buffer SDRAM 74 MHz #2 DLL 2 Actual HDTV Customer Example 74 MHz Internal Exactly Aligned 37 MHz Internal System Clock SDRAM Inside FPGA 23 Designing for 100+MHz

Precise Clock Mirroring 2 x system clock for board use Virtex FPGA 2 X 66 MHz Clock DLL 132 MHz Clock 24 Designing for 100+MHz

Clock Division w Divide clock by 1. 5, 2, 2. 5, 3, 4, 5, 8, or 16 — maintain synchronous edges CLKIn 200 MHz CLKout 200 MHz CLKDV 12. 5 MHz 25 Designing for 100+MHz

Multi-Standard Select. I/O GTL+ Micro. Processor 2. 5 V SSTL SRAM 1. 8 V SDRAM 5 V Tolerant FLASH Mixed Signal 5 V 3. 3 V LVTTL Busses/Backplanes (3/5 V PCI, ISA, GTL…) DSP 26 Designing for 100+MHz

Mix & Match Output Standards w User-supplied voltages determine output swing — 3. 3 V, 2. 5 V, 1. 5 V — one voltage per bank — a bank is half of a chip edge w Output characteristics are programmable on a per-pin basis — push-pull or open-drain — LVTTL drive strength – 2 -m. A to 24 -m. A sink and source current — LVTTL Slew rate 27 Designing for 100+MHz

Mix & Match Input Standards Internal Reference w Internal or user-supplied threshold voltage VREF Input — selectable on a per-pin basis Input — one user-supplied threshold voltage per bank Input w Programmable over-voltage Input protection Input — 5 -V tolerant or diode clamp to VCCO — selectable on a per-pin basis Input VREF 28 Designing for 100+MHz

SSTL Clock-to-Out With DLL w 200 MHz inter-chip data rate — SSTL 3, Class II — IOB register to IOB register Virtex FPGA 0. 3 ns D Q DLL 2. 8 ns 1. 9 ns Clock (Stub Series Transceiver Logic) 29 Designing for 100+MHz

SSTL Data Rate with DLL w 1. 3 ns measured clock-to-output delay — much lower noise than LVTTL Output standard = SSTL 3 Class 2 (OBUF_SSTL 3_II) Temp=100 C, Vdd=2. 375 V, Vcco=3. 3 V, Vtt=1. 5 V Waveforms: 1: CLKIN 2: DATA OUT (no DLL) 3: DATA OUT (DLL deskewed) Timing w/o DLL w/ DLL r->r r->f 3. 5 n 3. 8 n r->r r->f 1. 1 n 1. 3 n 30 Designing for 100+MHz

From FPGA to System Component ‘Redefining the FPGA’ x 1 CLK Chip 1 Cache SRAM (Mbytes) LVCMOS x 2 CLK SSTL 3 LVTTL Low Voltage CPU GTL+ SDRAM (133 MHz) Chip 1 High Speed System Backplane "Virtex moves FPGAs from glue to system component” - Ron Neale, EE Designing for 100+MHz 31

Power and Thermal Issues w Power and heat are serious concerns w All CMOS power consumption is dynamic — proportional to VCC 2 — proportional to capacitance — proportional to frequency w Virtex conserves power — 2. 5 -V supply voltage — small geometries and short interconnects reduce capacitance 32 Designing for 100+MHz

Virtex Power Consumption w Virtex is designed to conserve power — 100 MHz 16 -bit counters – 12. 5 MHz average transition rate – 6. 5 m. W per counter including clock distribution — 100 MHz 8 -bit counters – 25 MHz average transition rate – 5 m. W per counter including clock distribution XCV 300 XCV 1000 384 16 -bit Counters 2. 5 W Total 768 8 -bit Counters 3. 7 W Total 1536 16 -bit Counters 9. 8 W Total 3072 8 -bit Counters 14. 7 W Total 33 Designing for 100+MHz

Thermal Management w Temperature-sensing diode — matched to maxim MAX 1617 A/D — programmable alarms — similar to the Pentium II solution Virtex FPGA DXP DXN Maxim MAX 1617 SBMCLK SBMDATA ALERT 34 Designing for 100+MHz

Power Supply Decoupling w CMOS power-supply current is dynamic — current pulse every active clock edge w Peak current can be 5 x the average current — instantaneous current peaks can only be supplied by decoupling capacitors w Use one 0. 1 µF ceramic chip capacitor for each power-supply pin — low L and R are more important than high C — double up for lower L and R if necessary — use direct vias to the supply planes, close to the power-supply pins 35 Designing for 100+MHz

Virtex Configuration w New byte-wide Select. MAP mode — up to 528 Mbps at 66 MHz Control Logic (EPLD) Busy – simple handshake protocol — up to 400 Mbps at 50 MHz CS Address Configuration EPROM – no handshake required w Configuration bit-stream length — 0. 5 Mbits to 6. 1 Mbits Data WE, CS Virtex FPGA 36 Designing for 100+MHz

Volts, Amps, and Watts: Recap w PCB design issues — minimize capacitance for higher speed — terminate transmission lines to reduce ringing w Chip inputs and outputs — use DLLs to maximize I/O bandwidth — use Select. I/O to interface with different standards w Power and thermal considerations — use the sensing diode to manage chip temperature — decouple the power supply well w Configuration 37 Designing for 100+MHz

Designing for 100+ MHz. ü Volts, Amps, and Watts — PCB Signal Distribution — chip Inputs and Outputs — power and Thermal Considerations w Ones and zeros — logic Emulation w Bits and bytes — memory hierarchy 38 Designing for 100+MHz

Spending the 10 ns Budget w Fast logic requires fast function generators — signals often pass through several function generators w Routing delays must also be kept short — there are routing delays between every function generator w Arithmetic delays are important — carry chains often create critical paths 39 Designing for 100+MHz

You Don’t Have To Be An Expert w You don’t have to be an FPGA architecture expert to implement high-performance designs — the benefits of a good architecture automatic – all the logic goes faster – software provides easy access to the features w You can achieve high-performance only with a good FPGA architecture — a good FPGA empowers its users w You’ll design better if you know the architecture Designing for 100+MHz 40

Virtex CLB w Logic and arithmetic delay reduction demands improvements in the CLB w Virtex CLB is divided into two slices, each with: – 2 function generators – 2 flip-flops – 2 bits of carry logic Carry Fnct Gen Carry 41 Designing for 100+MHz

Fast Function Generators w Each function generator emulates 2 to 3 levels of logic — a 10 -level logic path typically requires 3 to 5 Function Generators in series — at 100 MHz, they must be less than 2 ns each including the routing w Virtex has 0. 6 -ns function generators — leaves 1. 4 ns for each route 42 Designing for 100+MHz

Connecting Function Generators w Some functions need several function generators — F 5 MUXs connect pairs of function generators – functions with 5 to 9 inputs — F 6 MUXs connect all 4 function generators – functions with 6 to 17 inputs Fnct Gen F 5 Fnct Gen F 6 43 Designing for 100+MHz

Fast Local Routing w Local routing provides fast interconnects — in a CLB, Function Generators connect with minimal routing delays — fast paths between adjacent CLBs increases flexibility Fnct Gen Fnct Gen Carry Carry 44 Designing for 100+MHz

Use Pipelining for Speed w Shorter clock periods means doing less each period — — create a pipeline structure pipeline stages operate concurrently more functions are done at the same time throughput increases w All function generators have output flip-flops — most pipeline support is “free” 45 Designing for 100+MHz

16 -Bit Pipeline in One LUT w In directly cascaded pipelines the flip-flops are not free Delay w One SRLUT can implement up to 16 bits of delay — shift data in and select the appropriate tap 16 -Bit Shift Register Select Output Input 46 Designing for 100+MHz

Fast Logic Needs Fast Routing w Our typical design with 3 to 5 CLBs needed an average routing delay of 1. 4 ns or less — the Virtex routing architecture delivers this performance w Delay is independent of direction — dependably short delays 47 Designing for 100+MHz

Go Farther, Faster w Virtex achieves its speed through a hierarchy of highly buffered routing resources — wires span 1, 2, or 6 CLBs w The Virtex routing architecture is designed for large arrays — today’s FPGAs are big… but tomorrow’s will be even bigger w Virtex is designed to maintain its performance Designing for 100+MHz 48

No Routing Congestion w For high-speed applications, routing must be dependably fast — not just capable of being fast w In the past, high device utilization has caused routing congestion — critical nets might be forced to meander w Virtex minimizes these problems — abundant resources prevent congestion If it needs to be fast, it will be fast – automatically! Designing for 100+MHz 49

Built-in Tri-State Busses w Bi-directional busses are supported directly by tri-state buffers built into each CLB — two drivers per CLB — segmentable every four CLB columns CLB CLB CLB 50 Designing for 100+MHz

Arithmetic – A Special Case w Adders, accumulators, counters, and comparators all depend on carry chains w Carry-chain logic is usually much deeper than the rest of the design — 32 levels for a 16 -bit ripple adder — too deep to use function generators at 100 MHz — arithmetic delays would limit performance w Dedicated carry logic provides the desired speed — 16 -bit adders can operate at up to 51 Designing for 100+MHz

Wide Arithmetic w 64 -bit adders would require 128 levels of logic — expensive complex carry schemes would be needed to preserve performance w Virtex minimizes the carry propagation delay — 100 ps per bit pair — zero routing delay between CLBs w Minimal performance loss for each extra bit 16 -bit adders operate at up to 200 MHz 64 -bit adders operate at up to 135 MHz 52 Designing for 100+MHz

Efficient Virtex Multipliers w Cascade vs. tree structure Delay — cascade simpler and smaller — tree is faster Cascade Tree Virtex Tree w Virtex gives the best of both worlds w 160 MHz clock rate for pipelined 16 x 16 multiplier Number of CLBs — as fast as a tree — smaller than a cascade 4 x 4 8 x 8 16 x 16 Cascade Tree Virtex Tree 4 x 4 8 x 8 16 x 16 Designing for 100+MHz 53

Fast Address Decoders w Wide address decoders could slow operation — wide AND gates with invertable inputs w Virtex carry-chain MUXs can act as AND gates — combine function generator ANDs w 64 -bit decoders operate at up to 155 MHz 0 1 0 1 54 Designing for 100+MHz

Speed Is Never Wasted w You can never have too much performance — excess performance can always be traded for size and cost reduction w Replace single-cycle functions with smaller multi-cycle versions — a 2 -cycle multiplier is half the cost of a single-cycle multiplier Reduce costs by designing down to the performance you need 55 Designing for 100+MHz

Creating a High-Speed Clock w Logic sometimes needs to operate faster than the available clock — multiple RAM accesses in a single cycle — low-speed PCB clock distribution for power or noise reduction w Virtex DLLs can double and redouble 2 X 2 X incoming clocks 45 MHz DLL 1 DLL 2 90 MHz 180 MHz 56 Designing for 100+MHz

Optimized for the Future w Deep sub-micron technology permits larger and larger array sizes — poses new circuit-design challenges — changes the rules of FPGA architecture w Across-chip routing is the most vulnerable — could easily limit design performance w Virtex is designed for long-term growth — even long, across-chip routes will remain fast Virtex is tomorrow’s FPGA … today! 57 Designing for 100+MHz

10 ns is Long Enough w Virtex CLBs can implement relatively complex functions in 10 ns — 0. 6 ns per 4 -input function generator w Virtex offers fast interconnections — even across-chip when fully utilized — fast tri-state buses w Support for very fast arithmetic operations — 16 -bit adders at 200 MHz 58 Designing for 100+MHz

Implement Designs Automatically w You don’t have to be an FPGA wizard to use Virtex w Virtex is optimized for automated implementation — uniform structure – efficient mapping/synthesis — ample routing – simple placement and no congestion — predictable performance – effective synthesis w IP cores speed design even more — validated functionality with guaranteed for 100+MHz Designing 59

Designing for 100+ MHz ü Volts, Amps, and Watts — PCB signal distribution — chip inputs and outputs — power and thermal considerations ü Ones and zeros — logic emulation w Bits and bytes — memory hierarchy 60 Designing for 100+MHz

100+ MHz Memory w Virtex memory operates up to 200 MHz w High-speed memory has two benefits — data storage – “work-in-progress” – input/output buffers, FIFOs — accelerating complex functions – store pre-computed values in look-up tables 61 Designing for 100+MHz

Data Storage Hierarchy Virtex supports 3 levels of memory hierarchy w On-chip Select. RAM+ — small-to-medium memories — 0. 6 -ns read access time w On-chip Block Select. RAM+ — larger memories — true dual-ported operation — 3. 3 -ns read access time w Fast Select. I/O interfaces to external RAM — DLL boosts memory bandwidth 62 Designing for 100+MHz

Select. RAM+ w Select. RAM+ uses CLB LUTs as user memory — — 16 -deep RAMs 32 -deep RAMs 16 -deep dual-ported RAMs 16 -deep shift registers w Cascadable for larger memories — 128 or more words deep — uses logic resources for expansion 63 Designing for 100+MHz

Block Select. RAM+ w Up to 32 dual-ported 4096 -bit RAM Blocks — synchronous read and write w True dual-port memory — each port has full read and write capability — different clocks for each port w Configurable aspect ratio — trade width for depth – 4096 x 1 bit to 256 x 16 bits — separate configurations for each port w Dedicated routing for memory expansion 64 Designing for 100+MHz

High-Speed Memory Interfaces w Select. I 0 and DLLs together provide fast access to many types of external memory w Xilinx currently offers two reference designs — fully synthesized — automatic placement and routing SDRAM … up to 125 MHz ZBTRAM … up to 143 MHz (Zero Bus-Turnaround) 65 Designing for 100+MHz

Input/Output Data Buffers w High-performance systems need data buffers to decouple internal operation from I/O activity — I/O may be sporadic (burst-mode busses) — I/O may be faster or slower — I/O may be wider or narrower w I/O buffers can take several forms — dual-ported RAMs — ping-pong buffers — FIFOs 66 Designing for 100+MHz

Dual-ported I/O Buffers w Block Select. RAM+ is ideal for I/O buffers — dual-ported operation – independent clocks and controls – bridges between clock domains – simultaneous read and write — port-specific aspect-ratio control – built-in rate/width conversions w Select. RAM+ provides similar benefits on a smaller scale 67 Designing for 100+MHz

Ping Pong Buffers w Ping-pong buffers are pairs of blocks that alternate between input and processing — self-addressing input — 0. 6 -ns read access w Larger buffers can use the dual-ported Block RAM — one address bit alternates read/write areas — 3. 3 -ns read access { 16 -Bit Shift Register Output { 16 -Bit Shift Register w SRLUT for small buffers. Read Address Select Input 68 Designing for 100+MHz

Small FIFOs in SRLUTs w Small FIFOs can be implemented in SRLUTs word count addresses the output data increment and enable SRLUT to Push Pop decrement to Pop Down enable only for both Word { w 16 -Byte FIFO in 4 CLBs Push — 16 x 16 in 6 CLBs — 200+ MHz w Expandable for deeper Input FIFOs Counter Up 16 -Bit Shift Register — — Output 69 Designing for 100+MHz

Large FIFOs in Block RAM Counter — add read and write address counters w Asynchronous push and pop Data En Full Push Block Select. RAM+ Addrs Output Data Addrs WE Control Logic Counter w Large FIFOs can use the Input dual-ported block RAM En Pop Empty w Different port sizes give rate-for-width conversion w Block RAM FIFOs can operate at up to 170 70 MHz Designing for 100+MHz

Pre-computing for Speed w Some functions are too complex for 10 -ns logic implementation — pipelining is not always possible w An alternative is to pre-compute all the possible results and store them in memory — select a result according to the inputs w Function time is independent of complexity — 0. 6 ns Select. RAM+ access time — 3. 3 ns Block Select. RAM+ access time w The function table can be smaller than the logic Designing for 100+MHz 71

Multiplication By A Constant w Sometimes, data has to be “scaled” — multiplied by a constant value Constant w A full multiplier is too expensive — it can multiply by a variable — unnecessarily general and too complex w Storing all multiples of the constant is a better alternative — smaller and much faster Input Multiplier Array Product Table Scaled Data 72 Designing for 100+MHz

16 -bit Scaler w A 216 -word product table is impractical — partition the input into nibbles – use 16 -word LUTs for nibble products – combine the partial products in adders w Roughly half the CLBs of a full Input multiplier — for a 16 -bit Coefficient: 36 CLBs vs. 62 CLBs w Pipeline the adders for extra speed LUT x 4096 LUT x 256 LUT x 16 Scaled Data LUT 73 Designing for 100+MHz

Changing the Constant w The SRLUT mode can be used to update the table — “push-only” stack — last 16 bits loaded define the table { Input Constant Register 16 -Bit Shift Register w A simple accumulator computes all products of a new constant Output Register Clear Load Change Constant 74 Designing for 100+MHz

Large Function Tables w Larger functions can be implemented in the Block Select. RAM+ — 12 -input functions — micro-coded state machines w Data tables can also be implemented — sine/cosine tables for DSP, for example — dual-ported access gives the sine and cosine simultaneously — a simple address offset gives 90º phase shift for accessing sine and cosine from a single table 75 Designing for 100+MHz

Block RAM/ROM Creation w CORE Generator software creates RAMs and ROMs — simple GUI interface w Initialization file is loaded into RAMs and ROMs at configuration time 76 Designing for 100+MHz

Memory Summary w Virtex has two kinds of internal memory — distributed Select. RAM+ for small RAMs — Block Select. RAM+ for larger RAMs w Select. RAM+ — — 0. 6 ns read access time 16 - and 32 -word RAMs 16 -word dual-ported RAMs 16 -word shift registers – sequential write/random-access read – FIFOs, pipelining, LUT functions, etc. . . 77 Designing for 100+MHz

Memory Summary w Dual-ported 4096 -bit Block Select. RAM+ — 3. 3 ns read access time — true dual-ported operation – both ports are read/write – ports can be clocked asynchronously — configurable aspect ratio – 4096 x 1 bit to 256 x 16 bits – configure ports differently for width/rate conversion w High-speed Select. I/O access to external RAM 78 Designing for 100+MHz

Designing for 100+ MHz üVolts, Amps, and Watts — DLLs and flexible I/O standards — fast inter-chip communication — simple rules for good signal integrity üOnes and zeros — fast logic and fast interconnect — dependable high performance ü Bits and bytes — distributed Select. RAM+ — dual-ported Block Select. RAM+ 79 Designing for 100+MHz

The Virtex Family The complete Virtex Data Sheet is on your App. Linx CD-ROM and at www. xilinx. com/partinfo/virtex. pdf 80 Designing for 100+MHz

Designing for 100+ MHz 81 Designing for 100+MHz