Design Kit Cool Runner-II Real Digital CPLDs

Design Kit

Cool. Runner-II Real. Digital CPLDs • Advanced. 18 process technology • JTAG In-System Programming Support – IEEE 1532 Compliant • Advanced design features – Multiple I/O standards – Multiple I/O banks – Input hysteresis – Extra clocking modes • New enhanced architecture allows design flexibility – 16 macrocells per function block – Global signals available at each macrocell – New Data. GATE and Cool. CLOCK features • Patented full-CMOS circuitry runs at extremely low power without compromising performance – Very low Static Icc

Design Kit • A complete, easy to use Cool. Runner-II CPLD design kit for: – Logic designers new to CPLDs – CPLD designers new to Xilinx – ASIC designers not aware of Cool. Runner-II advanced features • Simple and inexpensive demo board ready to use – – – Preprogrammed CPLD which flashes LED on power up Battery or AC outlet power source Inexpensive cable for programming LED's for simple testing Dual in line I/O header for easy connections

Cool. Runner-II Design Kit • Main box contains: – Digilent Cool. Runner-II PCB populated with – XC 2 C 256 -7 TQ 144 C and XC 9572 XL-10 VQ 44 C – Parallel printer download cable – Also supported are HW-PC 3/4 and Digilent JTAG 3 cable – Web. PACK CD – Full up design & programming software – Resource CD – Presentations, data sheets & technical information – Beginner’s Logic Design Book – AA battery holder

Digilent Board Description • Populated with – IC 1 • XC 9572 XL 10 VQ 44 C – IC 2 • XC 2 C 2567 TQ 144 C

Digilent Board Description • JTAG connection for programming CPLD

Digilent Board Description • Extra features – Pushbutton switch – LED's – Wall wart AC connection

Digilent Board Description • 18 -hole by 46 hole breadboard area for external component mounting • Dual-in-line header for easy connection to CPLD I/Os – IC 1 port C – IC 2 ports A, B, D C D B A

Digilent Board Description • Power jumpers – JP 1 • Battery or unregulated supply – J 8 • • VIO 2 VCORE VIO 1 Ground – JP 2, 3, 4 • Battery mode • Wall-plug mode • External mode

Digilent Board Description • Device Selection – JP 7, 8 • IC 1 or IC 2 or both • JTAG Programming – JP 6, 9, JP 5, 10 • Diagram of JTAG jumper settings

Collateral • Resource CD – Digilent board schematics, reference – – – manual Reference designs (link) Application notes (link) Data sheets (link) Presentations White papers • Ready to use Web. PACK design software – HDL or schematic designs – HDL bencher

Online Software Solutions • Free ISE Web. PACK™ – – – Downloadable desktop solution HDL / ABEL synthesis & simulation JTAG & 3 rd party EDA support Supports all Xilinx CPLD families Supports Spartan-II, IIE & III, Virtex-E & II (up to 300 K gates) FPGAs – Links to online purchasing • Free Web. FITTER™ – – – Easily fit designs for all Xilinx CPLDs online Accepts VHDL/verilog/abel & standard netlists Simple PLD & competitive conversions Fitting & timing reports Online price quotes for purchasing the best PLD silicon solution

Conclusion • Cool. Runner-II design kit offers an inexpensive method to test designs – 2 CPLDs with over 320 available Macrocells (XC 2 C 256 and XC 9572 XL) – Breadboard area • Maximum flexibility for other uses – I/O header for ease of connections for daughter cards – LED's • Functional test and user programmable – Pushbutton switch • Basic reset switch