Design Choices for Super Belle P Fischer I

Design Choices for Super. Belle P. Fischer, I. Peric, Ch. Kreidl, J. Kinzel Heidelberg University Design Choices for Super. Belle 1

Outline § Bumping constraints & consequences § Switcher § DCD Design Choices for Super. Belle 2

Philosophy § Must build a full detector in only 3 years Choose simple solution. Avoid risks Be ready to sacrifice performance for this § If possible, have ideas for better performance later Design Choices for Super. Belle 3

BUMPING

Bumping Constraints § Compare 3 possible ways to do the bumping: 1. Gold Studs 2. Buy chips with Pb. Sn bumps or similar (possible for UMC via SPIL wafer bumping service, IBM, …) 3. Get everything done by company Techno Min. pitch Bump Max. Pressure pad bumps / bump UBM Sensor Wafers Needed Au Stud 100 70 (60) 400 Bumped Chips 150 50 (? ) By vendor 50 15 >30 g no no No Low HD, (BN, HLL) 0 yes No Yes Med HD, (BN, HLL) 0 yes Yes High IZM, … Design Choices for Super. Belle Rework Cost Who 5

Consequences § Keep bump pitch at 150µm § Keep bump pad size at >65µm (best 70µm) § Restrict #bumps per chip to ~400 § Do not put anything under bump pads • A test chip with structures under bumps has been submitted § Start another wafer with dummy structures for yield tests as soon as chip geometries are fixed § Make tests with large number of gold studs (500) § Start development of UBM process @ HLL Design Choices for Super. Belle 6

SWITCHER

Belle. Switcher: What has changed? § What has changed w. r. t. ILC? • Pixels are larger in z Less channels per z needed • Pixels are wider in phi blocks of 4 even less pixels needed Only ~ 128 x 2 switcher channels for gate, clear required • Furthermore, we run continuously. Must decrease power § Discuss 3 possible control options: 1. Sequencer (as in Switcher 3) 2. Shift register (as in Switcher 2) 3. Multiplexer § Assume both voltages are switched within one chip. § For HV Switch choice: See later Design Choices for Super. Belle 8

Boundary conditions § 128 rows on half module § Module height ~ 10 cm § 12 µm trace pitch 2 x 64 traces x 12 µm = 1536µm § For two chips of 64 x 2 channels: • Routing all signals on M 1 requires width of 1. 5 mm for traces • Less if M 2 is used • 32 control signals in M 2 would need 400µm Design Choices for Super. Belle 9

1. Sequencer § Has been introduced in Switcher 3 • Can skip bad rows • Can read some parts more frequently • Can switch between programs (ROI readout, …) § Pros: • Very nice, flexible design (but what for? ) • Small number of control lines • Exists § Cons: • • • Complicated circuit (but exists) Still needs work to get floating logic SEU sensitive (-> Error bit, Hamming correction, … = work) Overhead makes sense only for large chips (>= 64 channels) A bit tricky to know that no clocks got lost… Design Choices for Super. Belle 10

2. Multiplexer § MUX with Enable line § Requires some control in DHP (minimum: just a counter) En 6 -En 0 P/N Gate Clear Str. P/N vddf / gndf Clear. Hi/Lo 7 x Level Shift Switch Level Shift Gate. Hi/Lo Monitor Design Choices for Super. Belle Write VDDA / GNDA 11

2. Multiplexer § Pros: • • • Very Simple NO storage (except few bias bits) no SEU problems Arbitrary sequences are possible (via Sequencer in DHP) Can do arbitrarily small chips Minimum Power (in digital part) § Cons: • ‘Larger’ number of (Address) lines: 7 differential lines Design Choices for Super. Belle 12

Pins Multiplexer § 7 x 2 En 6: 0 § 2 x 2 Strobe Clear and Gate § 2 x 2 § 1 § ~3 gndf, vddf Digital VLo, Vhi for Gate and Clear VDDA, GNDA ? ? ? Needed for HV part Monitor, for test only Slow control interface, reset § ~30 total Design Choices for Super. Belle Enable 13

3. Shift register § Re-inject serial input at every pass § Requires some control in DHP (inject every 128 clocks, monitor serial output for SEU) § Pros: • Simple • Only transient storage • Minimum number of control lines (SERIN, SEROUT(for monitor), CLK, RESET) § Cons: • Sequences limited. Cannot skip rows Design Choices for Super. Belle 14

More questions § Where to generate strobes for gate & clear? • In switchers from a reference clock ( strobes may vary slightly between rows) • In DHP ( strobes may vary slightly between sides / modules) • Externally: Best control. Only two extra differential lines! § How many channels per chip • • 128 64 32 16 1 chip 2 chips 4 chips 8 chips fanin too wide width of fanin is 1. 5 mm (one metal) / 0. 8 mm fanin 0. 8 mm / 0. 4 mm too many chips § Do we need decoupling? • Will put as much On-chip cap as possible. This may be enough • May require a few SMD caps Design Choices for Super. Belle 15

More questions § RC of sensor traces (dominated by trace, independent of W): • • Worst case model: R = L / W x 30 m C = e x e 0 x W x L / d t = ½ RC = e x L 2 x 0. 27 x 10 -9 ns / µm / d = 6 ns for L=7. 5 cm e = 4, d = 1µm § This is already at the limit for timing critical signals (strobes / clock) § This indicates that we should use M 2 for vertical traces (lower capacitance) Design Choices for Super. Belle 16

HV part § Ivan has improved new ‚SWITCHER 4‘ HV part by changing layout of enclosed ‚rad hard HV transistor‘ 50 V maximal voltage Floating logic Two outputs/channel Rad hard Relative fast Break before make L 0, 3, 17, 20 V supply/channel – 3 V and 17 V generated intenally Design Choices for Super. Belle 17

Annular DNMOS G D S S B n+ p+ p. G np- sub D

Simplified Schematic 20 V 17 V in out logic 3 V 0 V

Switcher 4 Test Chip - 64 channels - Clear and gate output - Pin compatible with switcher 2 - LVDS inputs - Shift register - Voltage regulators on chip

First Quick Measurements switches between 0 and 15 V switches between 15 and 0 V

Sw 4 measurements Some more switches between 10 and 0 V switches between 0 and 10 V

More. . switches between +7 and -7 V switches between +15 and +5 V

Sw 4 measurements Switching between 30 V and 0 V

Next steps § Decide on control mechanism § Try real layouts to solve Fanin – Control – Chip Geometry choice § Try to keep balcony as small as possible (<2 mm) § Irradiate HV switch in KA (setup ready) Design Choices for Super. Belle 25

DCD

New geometry § Goals: • Go to larger bump pitch (for possible Pn. Sn. . ) • Make gap between chips larger to accommodate errors in chip cutting (as observed in MPWs) • Make Y a multiple of 4 (simplify readout, Request by Hans) § Proposed Geometry: • 10 pixels in X, pitch = 150µm • 16 pixels in Y, pitch = 150µm Design Choices for Super. Belle 27

Routing for DCD with 10 x 16 pixels of (150µm)2 § Number of pixels: § Width of sensor part: § Bump pad width § Space for traces § Number of traces § Nominal gap 160 = 10(x) x 16 (y) 160 x 12. 5µm = 2000µm 70 µm 2000µm – 10 x 70µm = 1300µm / 12µm = 108 > 160/2 – OK 2000µm – 1525µm = 475 µm – OK 2000 µm 70 µm Design Choices for Super. Belle 28

Pad arrangement on chip § Chip Geometry: 3 x 1 MINIASICs = 1525 µm x 5000 µm § Have only analog stuff in upper pixels § Move digital stuff to the bottom DIG ITA LS TU FF • Synthesis • Use radiation hard library for a start 10 x 16 ANALOG parts (bump + cascode + current memory + ADC) Design Choices for Super. Belle Analog Power pads Digital Power Pads Digital Outputs Control 29

Readout options § Goals: • Be prepared for large current variation in matrix • Common mode subtraction (? ) • Faster readout without double sampling (? ) 1. Increase current range of current subtraction cell • Conceptually simple • Costs area 2. Increase dynamic range (= #bits) of ADC • Challenging • Very flexible • Readout without double sampling possible 3. DAC to subtract coarse current • Needs memory -> SEU issue • Readout without double sampling possible Design Choices for Super. Belle 30

Radiation Hard Standard cells § Cell height: 7. 44µm § Available cells so far: • • • • INV (Inverter) NAND 2 (2 -Input NAND) NOR 2 (2 -Input NOR) NOR 3 (3 -Input NOR) MUX 2 (2 -Input Multiplexer) XOR (Exclusive OR) GTINV (Gated Inverter) TGATE (Transmission Gate) DL (D Latch) RSFF (Set-Reset-Flip. Flop) DFF (D-Flip. Flop) DFRS (D-Flip. Flop with Set/Reset) FEED (Core Filler Cell) ENDCAP (Row Termination Cell) § Mixed mode support: NWELL and substrate connected to separate nets 31

Standard cell verification § A test design with several synthesized & automatically placed and routed designs has been submitted § All designs work as expected 32

Plans § Freeze Geometry § Choose FE concept § Submit 3 x 1 Mini. ASIC with bumps § Submit smaller chip with wire bond pads Design Choices for Super. Belle 33

Thank you Design Choices for Super. Belle 34

UMC 018: Possible Chip Dimensions § Submissions via Europractice: 3240 µ – 2 x 1525 µ = 190 µ • Full 5 x 5 mm 2 runs every 2 month, <14. 5 k€ • Mini. ASIC with blocks of (1. 525 mm)2 every 4 months, ~1. 8 k€ per block • ~2. 5 months delivery • Cost break even at 6 Mini. ASIC Blocks ! § Scribe Line: • Taking the possible Mini. ASIC dimensions (see figure) the scribe line + seal ring seems to be <=190µm • Dicing is obviously done with a pitch of 1525µm + 190µm • We must therefore assume that the real chip size is (190µm – blade width) more than expected. . . Design Choices for Super. Belle 1525 µ 3240 µ 4960 µ 35

Optimize for Phi resolution § We always hit two pixels in z § bricking pixels in Phi doubles resolution in Phi Switcher DCD z z=0 Design Choices for Super. Belle 36

Estimation of routing requirements (Switcher@End) § Assume • • 600 pixels in z 200 pixels in Phi Pixel width = 50µm Grouping of N pixels (N~4) § This gives • • Module width = 200 x 50µm = 10. 000 µm we have 200 * N drain lines we need 600 / N x 2 = 1200 / N gate + clear lines in total Total number of lines (drain + clear + gate) is 200 (N + 6 / N) The pitch p of these lines is 50 µm / (N + 6 / N) This has a (flat) minimum for N = sqrt(6) = 2. 5. . N=2: p = 10µm, 300 clear, 300 gate, 400 drain N=4: p = 9µm, 150 clear, 150 gate, 800 drain § For comparison: Normal Layout with N=4 requires p=12. 5µm Design Choices for Super. Belle 37

Possible Switcher Geometry (assume 16 x 2) B A P O W E R B A B P O W E R A B B B A B A B B A A B A B B A A B Power B A Addresses, Strobes A ~8 x 160µm ~ 1. 4 mm A B Clear / Gate to Matrix Design Choices for Super. Belle 38

Alternative Switcher Geometry (assume 16 x 2) B Clear / Gate to Matrix A B B A B A B A B B P O W E R A A B A B B A B B Design Choices for Super. Belle B A Digital signals on right side B 39