853fb4b8bae6af3ae32d0fc03462e07d.ppt

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DARPA Simulation and Synthesis of Quantum Circuits Igor L. Markov and John P. Hayes Advanced Computer Architecture Laboratory University of Michigan, EECS

Quantum Circuits Group @UMich PIs: Prof. Igor Markov & Prof. John Hayes l Postdoc: Dr. Ketan Patel (circuit testing) l Graduate Student Researchers & Fellows l l George Viamontes (simulation/Qu. IDDs) l Manoj Rajagopalan (simulation, synthesis by SA) l Do. Ron Motter (circuit complexity) l Smita Krishnaswamy (quantum clocks) l Parmoon Seddighrad (technology-specific opt. ) DARPA

High-level Assumptions and Goals l l Assumption: physicists [will] have “promising” technology prototypes Expectation: at 20+ qubits, design complexity becomes a serious issue l l Even at 20 bits, optimal logic synthesis is difficult Our job: improve the competitiveness of prototypes and facilitate applications l l Address specific design objectives and trade-offs Discover scalable design/simulation techniques Connect design techniques with applications Id new types of q. circuits and new applications DARPA

Our Expertise Computer Architecture l Electronic Design Automation / VLSI CAD l l Automated Synthesis of Logic Circuits l Formal Verification l Circuit Layout l Circuit Testing l Design & analysis of algorithms/heuristics l Including Algorithm Engineering (implementation, evaluation, integration) DARPA

Design Productivity Gap NTRS / ITRS: Design Productivity Gap is roughly 49% a year vs 21% a year l Is “quantum D. P. G. ” looming ? l DARPA

Fundamental Optimizations l Research in Design Automation targets core computational obstacles l E. g. , scalability in terms of runtime & QOR l Value in trying to solve “wrong” problems l Many optimization algorithms can be easily “re-focused” l Different objectives and constraints l Example: Simulated Annealing DARPA

Research Themes (1) l “From classical to quantum” l l l Use classical reversible circuits as [simple] test-bed Leverage and generalize known design techniques for classical circuits Simulation-driven design l l l Support for quantum circuit testing Ability to incrementally improve designs based on results of simulations/tests Ability to empirically evaluate quantum designs and algorithms without easily-provable properties DARPA

Research Themes (2) l New types of quantum circuits l Case-by-case automatic synthesis versus asymptotic constructions l l Empirical performance versus provable results l l l “Real life” vs theory (cf. synthesis of classical random logic) Separate design and simulation/test stages Example: sequential versus combinational New applications l l Enabled by automatic synthesis Leveraging new types of circuits, e. g. , sequential DARPA

Research Topics (1) l l Synthesis algorithms for classical logic as subroutines for quantum circuit synthesis Algebraic approaches to circuit synthesis l l E. g. , abstract and computational group theory Matrix factorizations: QR, ILU, CS and KAK Special-case synthesis, e. g. , Grover oracles Generic quantum circuit synthesis and reduction l l Dynamic programming Annealing and other heuristics DARPA

Research Topics (2) Automatic error correction during synthesis l Efficient simulation of quantum circuits l l Graph-theoretical algorithms based on common arithmetic sub-expressions (QUIDDs) l New types of quantum circuits l Quantum l clocks and other sequential circuits New [and old] applications l Quantum optimization algorithms (heuristics) l Memory-savvy versions of known algorithms DARPA

Remaining Part Of The Talk Synthesis of Reversible Logic Circuits and Applications to Grover’s Search l Synthesis of Quantum Circuits by Simulated Annealing l High-performance Simulation of Quantum Circuits using Qu. IDDs l DARPA

DARPA Optimal Synthesis of Reversible Logic Circuits Vivek V. Shende, Aditya K. Prasad, Igor L. Markov and John P. Hayes Advanced Computer Architecture Laboratory University of Michigan, EECS

Outline l Motivation l Real-world Applications l Asymptotically Zero-Energy circuits l Links to Quantum Computation Background l Theoretical Results l Synthesis of Optimal Circuits l An Application to Quantum Computing l DARPA

Real-world Applications Many inherently reversible applications l Info. is re-coded, but none is lost or added l l Digital signal processing l Cryptography l Communications l Computer graphics l Network congestion modeling DARPA

Links to Quantum Computation l l l Quantum operations are all reversible Every (classical) reversible circuit may be implemented in quantum technology, with overhead “Pseudo-classical” subroutines of quantum algos l l Can be implemented in classical reversible logic circuits Grover’s search : DARPA

Outline Motivation l Background l l Reversibility l Permutations l Known Facts Theoretical Results l Synthesis of Optimal Circuits l An Application to Quantum Computing l DARPA

Reversibility in Logic Gates l Definition: reversible logic gate l l l Examples l l l #input wires = #output wires Permutes the set of input values Inverter 2 -input, 2 -output SWAP (S) gate k-CNOT gate l l l (k+1)-inputs and (k+1)-outputs Values on the first k wires are unchanged The last value is flipped if the first k were all 1 DARPA

Reversibility in Logic Circuits l Definition: A combinational logic circuit is reversible iff l It contains only reversible gates l It has no fan-out l It is acyclic as a directed multi-graph l Theorem: A reversible circuit must l Have as many input wires as output wires l Permute the set of input values DARPA

A Reversible Circuit and Truth Table x 0 0 1 1 y 0 0 1 1 z 0 1 0 1 x’ 0 0 1 1 y’ 0 0 1 1 z’ 0 1 1 0 Equivalent to a single CNOT gate DARPA

Circuit Equivalences Circuit equivalences: useful in synthesis l More will be shown later l DARPA

Reversible Circuits & Permutations l A reversible gate (or circuit) with n inputs and n outputs has l l 2 n possible input values 2 n possible output values The function it computes on this set must, by definition, be a permutation l The set of such permutations is called S 2 n l DARPA

Basic Facts About Permutations l Permutations are multiplied by first applying one, then the other l example: l (1, 2)◦(2, 3) = (1, 3, 2) A transposition l permutes exactly two elements l does not change any others l Every permutation can be written as a product of transpositions DARPA

Even Permutations Consider all possible decompositions of a permutation into transpositions l Theorem: The parity of the number of transpositions is constant l Definition: Even permutations are those for which the number of transpositions is even l DARPA

Known Facts l Fact 1: Consider a reversible circuit l l n+1 inputs and n+1 outputs Built from gates which have at most n inputs and n outputs Must compute an even permutation Fact 2: A universal gate library l CNOT, and TOFFOLI (“CNT”) l Temporary storage may be required DARPA

Temporary Storage DARPA

Outline Motivation l Background l Theoretical Results l l Zero-storage Circuits l Reversible De Morgan’s Laws Synthesis of Optimal Circuits l An Application to Quantum Computing l DARPA

Minimizing Temporary Storage l Consider CNT circuits l Theorem: even permutations computable by circuits without temporary storage l Theorem: odd permutations computable with one line of temporary storage Same holds for NT and CNTS circuits l The proof is constructive and may be used as a synthesis heuristic l DARPA

Outline of Proof Explicitly construct a circuit to compute an arbitrary pair of disjoint transpositions (A, B) (C, D) is okay; (A, B) (B, C) is not l Pick an even permutation l Decompose it into transpositions l l Will have an even number of transpositions Pair these up, guaranteeing disjointness l Apply construction to each pair l DARPA

Flowchart of Proof DARPA

Reversible De Morgan’s Laws (1) l De Morgan’s Laws l Can send inverters to inputs in AND/OR/NOT circuits l Reversible De Morgan’s Laws l l Can send inverters to inputs in CNT circuits Rules exist to move TOFFOLI and CNOT gates l l However, it is not always possible to push all CNOT gates to the inputs Oddly enough, all CNOT gates can be pushed to the “middle” of the circuit DARPA

Reversible De Morgan’s Laws (2) DARPA

Reversible De Morgan’s Laws (3) DARPA

Outline Motivation l Background l Theoretical Results l Synthesis of Optimal Circuits l l Optimality l DFID Search Algorithm l Circuit Libraries l An Application to Quantum Computing DARPA

Optimality l The cost of a circuit is its gate count l Other l cost functions can be considered Definition: optimal reversible circuit l no circuit with fewer gates computes the same permutation l Theorem: a sub-circuit of an optimal circuit is optimal l Proof: otherwise, can improve the sub-circuit DARPA

The Search Procedure l Depth First Iterative Deepening Search l Checks all possible circuits of cost 1, then all possible circuits of cost 2, etc… l Avoids the memory blowup of BFS Still finds optimal solutions (unlike DFS) l Checking circuits of cost less than n is much faster than processing cost-n circuits l DARPA

Dynamic Prog + Circuit Libraries l DFID search requires a subroutine to check all circuits of cost n, for arbitrary n l Called iteratively for 1…n Only need to check locally optimal circuits l Build optimal circuit library bottom up by DP l l Index optimal circuits by computed permutation l In practice use hash_map datastruct from STL DARPA

Synthesis Algorithm DARPA

Empirical Circuit Synthesis Consider all reversible functions on 3 wires (8! = 40, 320 functions) l For each gate library from N, C, T, NC, CT, NT, CNTS l l Is it universal? l How many functions can it synthesize? l How long does it take to synthesize circuits? l What are largest optimal circuits? DARPA

Optimal Circuit Sizes Size N C T NC CT NT CNTS 12 11 10 9 8 7 0 0 0 0 0 0 14 0 0 6 386 47 1690 8363 12237 9339 5097 0 0 577 10253 0 0 32 6817 6 0 215 1688 2262 17049 17531 5 4 3 2 1 0 0 0 1 3 3 1 8 1 24 60 51 24 6 1 168 1 0 5 9 6 3 1 24 1 474 393 187 51 9 1 1344 30 1784 845 261 60 9 1 5040 215 870 296 88 24 6 1 40320 97 8921 2780 625 102 12 1 40320 40 11194 3752 844 135 15 1 40320 15 Total Time, s DARPA

Largest Optimal Circuits l Note that purely quantum gates can enable smaller circuits l John A. Smolin, "Five two-bit quantum gates are sufficient to implement the quantum Fredkin gate“, PRA 53(4), 1996, pp. 2855 -2856 l Q. Circuit Synthesis via the Ring Normal Form (papers by Thomas Beth and Martin Röttler) DARPA

Why Circuit Libraries? l Large speedup over straight DFID l Can be calculated from previous table l Calculated values are very large l In practice, the table cannot be generated in several hours without circuit libraries l With libraries, the table takes less than 10 min DARPA

Outline Motivation l Background l Theoretical Results l Synthesis of Optimal Circuits l An Application to Quantum Computing l l Grover’s Search l Pseudo-classical Synthesis DARPA

Quantum Circuits Necessarily reversible l Bit-lines are now qubits l All classical reversible gates still allowed l l Many other gates used as well l Circuit equivalences for reversible gates are still valid ! DARPA

Grover’s Search l A quantum algorithm for associative search (input is not sorted) l l Runs in time O(√N) l l Search criterion: a classical one-output function f classical algorithms require (N ) time Requires a subroutine that l changes the phase (sign) of all basis states (bit-strings) that match the search criterion f DARPA

Grover Oracle Circuits l To change the sign of a bit-string l l l Initialize a qubit to |0> - |1> Compute the classical one-output function f XOR the qubit with f Whenever f =1, the sign (phase) will change Thus, the design of Grover search circuits for a given f l Is reduced to reversible synthesis l Can be solved optimally by our methods DARPA

Sample Grover Circuit DARPA

ROM-based Circuits l Desired circuits must alter phase of basis states l l Previous work studied ROM-based circuits l l All bits except one must be restored to input values Constraint: ROM qubits can never change B. Travaglione et al. , 2001, http: //xxx. lanl. gov/abs/quant-ph/0109016 Theorems + heuristic synthesis algorithms Our work: synthesis of pseudo-classical circuits l l l 3 read-only “ROM” wires that can never change 1 wire that can be changed during computation, but must be restored by end 1 wire on which function is computed DARPA

Synthesis Algorithms Compared l Heuristic synthesis of ROM-based circuits l Proposed by Travaglione et al, 2001 l Based on XOR-sum decomposition (“XOR”) l Imposed a restriction: at most one control bit per gate can be on a ROM bit l Optimal synthesis (as described earlier) l with restriction from Travaglione (“OPT T”) l without this restriction (“OPT”) DARPA

Sizes of 3+2 ROM-circuits Size 0 XOR 1 OPT T 1 OPT 1 Size 1 2 3 4 5 4 6 4 4 12 7 21 35 36 28 6 7 8 9 10 11 12 18 12 6 12 19 16 10 21 24 29 33 44 46 22 28 36 35 21 7 1 0 13 14 15 16 17 18 19 20 21 22 23 24 25 26 XOR 8 10 16 19 12 6 12 18 12 4 4 6 4 1 OPT T 5 1 0 0 0 OPT 0 0 0 0 DARPA

Discussion of Empirical Results The XOR-SUM heuristic is sub-optimal l All methods able to synthesize all 256 fns l l “OPT T” can synthesize as many as “OPT”: B. Travaglione et al. , 2001 l “OPT” results symmetrical about 5 -6 gates l Function x requires one fewer gate than 256 -x l Explanation yet to be found l “XOR” results symmetrical about 13 gates DARPA

Conclusions Classical reversible circuits as special-case quantum circuits l Existence theorems l Reversible De Morgan’s laws l l Future l research on optimization heuristics Algorithm for synthesis of optimal circuits l Applicable l to Grover’s search See details in quant-ph/0207011 l. A more detailed version will posted by 09/22 DARPA

DARPA Quantum Circuit Synthesis by Simulated Annealing Manoj Rajagopalan, Igor L. Markov, and John P. Hayes Advanced Computer Architecture Laboratory University of Michigan, EECS

The Problem l Synthesize a quantum circuit l Using gates from the given library l To achieve a specified unitary matrix (can also consider effects of measurement) l Very few qubits are considered l All matrices are still very small l Yet, there can be many of gates DARPA

Synthesis Techniques Exhaustive Search l Matrix Factorization (QR, CS, ILU, KAK) l l [Cybenko 2000] l Dynamic Programming + Branch & Bound l l [Shende. PMH 2002], quant-ph/0207001 Genetic Algorithms l l uses QR [Williams. G 1999, Yabuki. I 2001] Simulated Annealing: this work DARPA

Simulated Annealing l Stochastic algorithm l l l form of local search for solving optimization problems Annealing: heating and gradual cooling to toughen (metal or glass) and reduce brittleness Simulated annealing (combinatorial optimization) l Objective function ~ energy of system l Minimized by simulating Brownian motion with decreasing temperature l Moves randomly selected, good ones accepted, and bad ones accepted in some cases l Probability of accepting bad move = e (- cost / T) DARPA

Simulated Annealing for Q. S. l Represent circuit synthesis as an optimization problem l Solution space: l Quantum circuits (circuit topology + gate types) l Constraints: l Output must match specification for given input l Gates from given library l Objectives: l Minimize number of gates l Minimize the error (in some norm) DARPA

A Naive Annealer + Extension Consider individual circuits, one at a time l Evaluate matrix product of all gates l l Compute l the error Better idea: incremental evaluation l Add/remove/change one gate at a time l Incrementally compute matrix product DARPA

Incremental Perturbation Perturb gates at ends of circuit l Effect of adding and removing single gates realized by qubit-wise multiplication l Asymptotic improvement per move l l Suppose we have N gates l Incremental evaluation: O(1) time l Evaluation from scratch: O(N) time DARPA

Simulated Annealing Procedure Initial solution: empty circuit (Id matrix) l Choose initial temperature (…), final T = 0 l Adopt a temp. schedule (linear, geometric) l Single-qubit move and CNOT moves l l At either end of current circuit, select (with equal probability) from l No change (NOP) l Add a gate (ADD) l Remove a gate (REM) l Replace a gate (REP) DARPA

Simulated Annealing Procedure l l Make a random move Evaluate error of new circuit l l l If error <10 -6, consider synthesis complete Else evaluate cost: weighted sum of error and #gates If a move improves cost, then accept it Else accept move with probability exp (- cost / T) Must accept some bad moves to avoid local minima l l T=0 means greedy Low-temperature annealing cannot climb hills well DARPA

Simulated Annealing Procedure Reduce temp. according to schedule l Repeat move selection, acceptance… l Perform iterations until final temperature is reached l DARPA

Implementation Platform AMD Athlon 1. 2 GHz processor l Debian Linux l C++ (g++ v 2. 95. 4 –O 3) l DARPA

Quantum Gates DARPA

Test 1: H-X-Z gate circuits Hadamard (H), Not (X) and Phase shift (Z) l Optimal one-qubit circuits typically require up to 3 gates per qubit l Targets for synthesis: l l randomly l generated circuits with 5 qubits Results averaged over 100 independent starts DARPA

H-X-Z circuit results (5 qubits) Library Min Size (# gates) Avg Size Avg Time (# gates) (s) Success rate HXZ 6 17 0. 60 100 % H X Z½ 7 27 5. 53 82 % HZ 8 23 1. 82 99 % HX 10 52 3. 48 81 % H Z½ 12 29 4. 23 81 % DARPA

H-X-Z circuit results Reasonably small runtimes l Near-optimal (? ) circuits found l l We were not able to find better circuits by paper & pencil calculations l In principle, can change the gate library DARPA

Test 2: Teleportation circuits ([Williams. G 1999] & [Yabuki. I 2001] Circuits with CNOT gates R S S L T Sender Receiver DARPA

Quantum Gates R=ZH=HX L=HZ=XH R = L† S = X Z½ X DARPA

Synthesis of Sender-Circuit Gate Library Min Size (# gates) Avg Size Avg Time Success (s) Rate (# gates) L, CNOT, R 4 53 11. 23 95 % CNOT, H, X 20 125 31. 43 51 % CNOT, H, Z 8 162 38. 46 45% DARPA

Receiver Circuit Synthesis Gate Library S, CNOT, T Min Size Avg Time Success Rate (# gates) (s) 4 5 0. 05 100 % (83% opt) H, CNOT, Z½ 4 6 0. 11 100 % (68% opt) H, CNOT, Z½ Z¼, X 3 5 0. 22 100 % (44% opt) DARPA

Teleportation: Previous Work l Williams and Gray (Genetic Algos) l Both circuits with 4 gates, 100% success rate l Initial population size is 100 circuits l Requires 4 generations - 2640 circuit evaluations - on average l Yabuki and Iba (Genetic Algos) l Sender circuit - 4 gates, Receiver - 3 gates l Simplify the problem by exploiting features l Requires 350 generations of 5000 candidates on average DARPA

Conclusions l Simulated annealing l Promising heuristic for synthesis of q. circuits l Benefits from incremental evaluation l Reasonably fast l Competitive with Genetic Algorithms (better? ) l Flexibility l Gate libraries can be easily changed (e. g. , over-specified) l Various optim. objectives can be addressed l Ditto for constraints DARPA

On-going Work l More focus on minimizing the number of gates l l Account for more physical phenomena l l l Circuit equivalence up to global phase Adaptive move-type selection l l So far, mostly tried to find a circuit quickly Based on how successful previous moves were Temperature schedule, initial temperature More challenging synthesis problems l l Add Toffoli gates (increased inter-qubit interaction) Continuous gate libraries (single-paramater gates) DARPA

References 1. G. Cybenko, “Reducing quantum computations to elementary unitary operations”, Comp. in Sci. and Engin. , pp. 27 -32, March/April 2001. 2. V. V. Shende, A. K. Prasad, I. L. Markov, J. P. Hayes, “Reversible Logic Circuit Synthesis”, to appear in Proc. ACM/IEEE Intl. Conf. Comp. -Aided Design, Nov. 2002 3. C. P. Williams, A. G. Gray “Automated design of quantum circuits”, In QCQC’ 98 LNCS 1509, pp. 113 -125, Springer-Verlag, 1999. 4. T. Yabuki, H. Iba, “Genetic Algorithms for quantum circuit design –Evolving a simpler teleportation circuit-”, In Late Breaking Papers at the 2000 Genetic and Evolutionary Computation Conf. , Las Vegas, NV, pp. 425 -430, 2000. DARPA

DARPA High-Performance Simulation of Quantum Computation using Qu. IDDs George F. Viamontes, Manoj Rajagopalan, Igor L. Markov, and John P. Hayes Advanced Computer Architecture Laboratory University of Michigan, EECS

Problem l Simulation of quantum computing on a classical computer l Requires exponentially growing time and memory resources using standard linear algebra Goal: Improve classical simulation l Solution: Compress redundancy in relevant matrices and vectors l DARPA

Redundancy in Quantum Computing Matrix representation of quantum gates contain block patterns l The Tensor (Kronecker) Product l l Create state vectors and operators involving multiple qubits l Propagates block patterns in vectors and matrices DARPA

Example of Propagated Block Patterns Only TWO distinct blocks! DARPA

Compressed Representations That Capture Structure l l We could try Lempel-Ziv compression, but manipulating compressed data is difficult Try using compression based on structure that we understand, e. g. , l l l Complex get. Matrix. Element(int row, int col, int qubits) { return pow ( sqrt(2) , qubits ) *( inn. Prod. Mod 2 ( row, col ) ? 1 : -1 ); } Still difficult do manipulate Consider a decision tree based on row & col l No exponential compression (? ) DARPA

*BDDs: Data Structures that Exploit Redundancy l Binary Decision Diagrams (BDDs) exploit repeated sub-structure l l l Different variants: ROBDDs, ZDDs, ADDs, FDDs, EVDDs, … Common idea: bottom-up merging of nodes in decision trees Example: f = a AND b f a Assign value of 1 to variable x b Assign value of 0 to variable x 1 0 DARPA

*BDDs: Data Structures that Exploit Redundancy l BDDs have been used to simulate classical logic circuits [Lee 59, Bryant 86] l l A circuit can be “simulated” on all input values at once BDDs made useful by fast operations l l Bryant’s main contribution: ROBDDs A fixed ordering of nodes + reduction rules Potentially less compression, but faster algorithms l Used in most *DD data structures, including Qu. IDDs l l Compare to “read-once branching programs” DARPA

Basic BDD Operations [Bryant 1986] ( |A| = number of nodes in BDD A ) l Most BDD operations are based on recursive procedures: ITE, Apply, etc l l Typically take two or three BDDs as arguments Apply(A, B) has space and time complexity Apply is an algorithmic form of Boole’s Expansion Different types of *DDs optimize operations for specific contexts and reduction rules, e. g. , l EVDDs (edge-valued), ZDDs (zero-suppressed), etc DARPA

Linear Algebra via BDDs l Variants of BDDs have been used to represent matrices and vectors Algebraic Decision Diagrams (ADDs) treat variable nodes as matrix indices [Bahar 93] l ADDs compress repeated block patterns in matrices and vectors l Linear Algebraic operations can be performed as ADD traversals (i. e. , w/o decompression) l l From general to specific: l MTBDDs ADDs Qu. IDDs DARPA

Quantum Information Decision Diagrams l Quantum Information Decision Diagrams (Qu. IDDs) l l l Similar structure to ADDs Three types of nodes l l An application of ADDs to the quantum computing domain Row, Column, Terminal Use modified ADD operations DARPA

Qu. IDD Structure l BDD variable ordering l Defines the order in which different node types appear Qu. IDD variable ordering interleaves row and column variables l Terminal nodes are always last l DARPA

Quantum Circuit Simulation Issues Specific to Qu. IDDs l Use state-vector representation l In principle, Qu. IDDs can also model the density-matrix representation Avoid matrix-matrix mult. (for efficiency) l Tensor products and matrix-vector multiplications are performed l l Are very efficient DARPA

Qu. IDD Vectors Use column and terminal variables l Represent qubit state vectors l Some examples: l f T 00 01 01 10 10 11 11 DARPA

Qu. IDD Matrices Use row, column, and terminal variables l Represent gates / unitary matrices l l There is no requirement for unitary matrices, l Constant factors can be stored separately DARPA

Example: 2 -Qubit Hadamard Qu. IDD f 00 01 10 11 DARPA

Qu. IDD Operations l Based on the Apply algorithm [Bryant 1984, Clarke. Et. Al 1996] l Construct new Qu. IDDs by traversing two Qu. IDD operands l Perform “op” at terminals (op can be *, +, etc. ) l The variable ordering directs the traversal l General Form: f op g where f and g are Qu. IDDs, and x and y are variables in f and g, respectively DARPA

Tensor Product l To compute A B l Every element of a matrix A is multiplied by the entire matrix B l Qu. IDD implementation: uses Apply l Operands are A and B l Variables of operand B are shifted l “op” is defined to be multiplication DARPA

Matrix Multiplication l l l A modified form of the Apply function Dot-product can be done on Qu. IDDs without decompression l “Skipped” nodes are counted l A factor of 2#skipped is multiplied by dot-products Qu. IDD Implementation l Modified ADD matrix multiply algorithm [Bahar 93] l Support complex number terminals l Account for row/column variable ordering DARPA

Other Operations l Matrix addition l Call l Scalar operations l. A l to Apply with “op” set to addition special one-operand version of Apply Qubit measurement l. A combination of matrix multiplications, tensor products, and scalar operations DARPA

Simulation of Grover’s Algorithm Qu. IDDPro was tested by running instances of Grover’s Algorithm l Results indicate linear memory usage in many cases l l Any circuit with an oracle whose Qu. IDD form is polynomial in # of qubits DARPA

Sample Circuit Representation |0> H H H . . . |1> H Oracle . . . Conditional Phase Shift . . . H DARPA

Simulation of Grover’s Algorithm l # iterations computed [Boyer. Et. Al 96] l# iterations = l Where l M=# of solutions, 2 q=# of elements in data set l Exponential runtime on a quantum computer l When M is small, the number of iterations is exponential in the number of qubits DARPA

Projected Grover Iterations l SANITY CHECK: Make sure that the number of iterations predicted by Boyer et al. results in the highest probability of measuring the item(s) to be searched DARPA

Experiment versus Predictions DARPA

Simulation Results for Grover’s Algorithm l Linear growth of Qu. IDDs in Grover’s l Number of nodes in Qu. IDDs shown algo DARPA

Grover’s Algorithm: Results using Oracle 1 “searches” for one element in the data set l Oracle polynomial in size l Linear memory asymptotics l Run-times are extremely low vs Matlab l DARPA

Grover’s Algorithm: Results using Oracle 1 Linear growth with Qu. IDDPro DARPA

Grover’s Algorithm: Results using Mod-1024 Oracle Finds elements in the data set whose 10 least significant bits are 1 l Useful in demonstrating asymptotics l l Memory and runtime are governed purely by the size of the system DARPA

Grover’s Algorithm: Results using Mod-1024 Oracle l For data up to n=25 qubits, linear least-squares regression shows that memory (MB) grows as 7. 5922 + 0. 0410 n Linear growth with Qu. IDDPro DARPA

Conclusions and Future Work l Asymptotic performance when Qu. IDD form of oracle is poly-sized l l Far more efficient than other classical simulation techniques l l MATLAB, Blitz++: (2 n) We plan to simulate other algorithms using Qui. DD Pro (+ inject errors) l l Qu. IDDPro: ~1. 66 n; Ideal Q. Computer: ~1. 41 n A simulation of Shor’s algorithm operational Details in quant-ph/0208003 DARPA

References [1] C. Y. Lee, “Representation of Switching Circuits by Binary Decision Diagrams”, Bell System Technical Jour. , 38: 985 -999, 1959. [2] R. Bryant, “Graph-Based Algorithms for Boolean Function Manipulation”, IEEE Trans. On Computers, vol. C-35, pp. 677 -691, Aug 1986. [3] R. I. Bahar et al. , Algebraic Decision Diagrams and their Applications”, In Proc. IEEE/ACM ICCAD, pp. 188 -191, 1993. [4] E. Clarke et al. , “Multi-Terminal Binary Decision Diagrams and Hybrid Decision Diagrams”, In T. Sasao and M. Fujita, eds, Representations of Discrete Functions, pp. 93 -108, Kluwer, 1996. [5] M. Boyer et al. , “Tight Bounds on Quantum Searching”, Fourth Workshop on Physics and Computation, Boston, Nov 1996. DARPA