CSE 331 Computer Organization and Design Fall 2007

CSE 331 Computer Organization and Design Fall 2007 Week 13 Section 1: Mary Jane Irwin (www. cse. psu. edu/~mji) Section 2: Krishna Narayanan Course material on ANGEL: cms. psu. edu [adapted from D. Patterson slides] CSE 331 W 13. 1 Irwini Fall 2007 PSU

Head’s Up q Last l Multicycle MIPS datapath and control path implementation, microprogramming q This l week’s material Input/Output – dealing with exceptions and interrupts - Reading assignment – PH: 5. 6, 8. 1, 8. 5, A. 7 -A. 8 q Next l week’s material Intro to pipelined datapath design - Reading assignment – PH: 6. 1 q Reminders l l CSE 331 W 13. 2 HW 7 is due Monday, Dec 3 rd (by 11: 55 pm) Quiz 7 closes Tues. , Dec 4 th (by 11: 55 pm) Final Exam is Tues. , Dec 18 th, 10: 10 to noon, 112 Walker Dec. 12 th deadline for filing grade corrections/updates Irwini Fall 2007 PSU

Well, surely a higher college GPA ought to be correlated with career success … the data didn’t bear this out. … fast-trackers have identifiable qualities and show definite trends. One quality is a whateverit-takes attitude … a willingness to do whatever it takes to make a project succeed … If that means working weekends … they do it. Another quality is a solid, unflappable understanding of all the technologies they are using or developing. … Finally, these high-output types seemed to innately grasp that they are members of a large team … they are the ones always helping everyone else. The Pentium Chronicles, Colwell, pg. 140 CSE 331 W 13. 3 Irwini Fall 2007 PSU

Major Components of a Computer Processor Control Devices Memory Output Datapath q Important l l CSE 331 W 13. 4 l Input metrics for an I/O system Performance Compatibility Expandability and diversity Dependability Cost, size, weight Irwini Fall 2007 PSU

Input and Output Devices q I/O l l l devices are incredibly diverse with respect to Behavior – input, output or storage Partner – human or machine Data rate – the peak rate at which data can be transferred between the I/O device and the main memory or processor Magnetic disk Graphics display CSE 331 W 13. 5 Behavior input output input or output storage Partner human machine Data rate (Mb/s) 0. 0001 0. 0038 3. 2000 100. 0000 -1000. 0000 machine 240. 0000 -2560. 0000 output human 800. 0000 -8000. 0000 8 orders of magnitude range Device Keyboard Mouse Laser printer Network/LAN Irwini Fall 2007 PSU

Input/Output in SPIM via System Calls q SPIM provides a small set of operating-system-like services through the syscall instruction l l Load the system call code into register $v 0 and the arguments into registers $a 0 trhough $a 3 Return values are put in register $v 0 Service Code Args print_int $a 0 = integer 1 print_string $a 0 = string 4 read_int 5 read_string $a 0 = buffer, 8 $a 1 = length print_char 11 $a 0 = char read_char 12 CSE 331 W 13. 6 Results integer in $v 0 char in $a 0 ? $v 0? Irwini Fall 2007 PSU

Communication of I/O Devices and Processor q How l the processor directs the I/O devices Special I/O instructions - Must specify both the device and the command l Memory-mapped I/O - Portions of the high-order memory address space are assigned to each I/O device. Read (lw) and writes (sw) to those memory addresses are interpreted as commands to the I/O devices - Load/stores to the I/O address space done only by the OS q How the I/O device communicates with the processor l Polling – the processor periodically checks the status of an I/O device to determine its need for service - Processor is totally in control – but does all the work - Can waste a lot of processor time due to speed differences l Interrupt-driven – the I/O device issues an interrupts to the processor to indicate that it needs attention CSE 331 W 13. 7 Irwini Fall 2007 PSU

“Real” I/O in SPIM q SPIM supports one memory-mapped I/O device – a terminal with two independent units l l Transmitter writes characters to the display Receiver reads characters from the keyboard Processor Devices Control Transmitter Datapath CSE 331 W 13. 8 Memory Receiver Irwini Fall 2007 PSU

Review: MIPS (spim) Memory Allocation Memory Mem Map I/O $sp Kernel Code & Data fffffffc f f 0000 8000 0080 7 f f e f f fc Stack 230 words Dynamic data $gp Static data 1000 8000 ( 1004 0000) 1000 0000 User Code PC CSE 331 W 13. 9 Reserved 0040 0000 Irwini Fall 2007 PSU

Terminal Receiver (Input) Control with SPIM q Input is controlled via two memory-mapped device registers (i. e. , each is a special memory location) 7 Receiver data (0 xffff 0004) 0 unused received byte from keyboard (read only) 1 0 Receiver control (0 xffff 0000) unused interrupt enable l l ready (read only) The keyboard inputs into the Receiver data register which sets the ready bit in the Receiver control register (i. e. , the keyboard input is ready to be read by the program) Reading the next input character from the Receiver data register resets the ready bit in the Receiver control register CSE 331 W 13. 10 Irwini Fall 2007 PSU

Terminal Output Control with SPIM q Output is controlled via two memory-mapped device registers (i. e. , each is a special memory location) 7 Transmitter data (0 xffff 000 c) 0 unused transmitted byte to display 1 0 Transmitter control (0 xffff 0008) unused interrupt enable ready (read only) The display outputs the Transmitter data register character which sets the ready bit in the Transmitter control register (i. e. , the display is ready to accept a new output character) l Writing the next character to output into the Transmitter data register resets the ready bit in the Transmitter control CSE 331 W 13. 11 register Irwini Fall 2007 PSU l

MIPS I/O Instructions q MIPS has 2 coprocessors: Coprocessor 0 handles exceptions including input and output interrupts, Coprocessor 1 handles floating point l Coprocessors have their own register sets so have instructions to move values between these registers and the CPU’s registers mfc 0 rd, rt 0 x 10 0 mtc 0 rt, rd 0 x 10 CSE 331 W 13. 12 Register # Use Bad. VAddr 8 bad mem addr Count 9 timer Compare 11 timer compare Status 12 intr mask & enable bits Cause 13 excp type and pending intr’s EPC 14 addr of instr causing excp #move from coprocessor 0 rt rd 0 0 #move to coprocessor 0 4 rt rd 0 0 Irwini Fall 2007 PSU

Polling in SPIM q Be sure that memory-mapped I/O is enabled (through the PCSpim “Settings” dialog box) li li mtc 0 I 1: I 2: CSE 331 W 13. 13 $t 0, $t 1, $t 2, $t 3, 0 xffff 0000 0 xffff 0004 0 xffff 0008 0 xffff 000 c #recv ctrl #recv data #trans ctrl #trans data $zero, $12 #disable interrupts lw andi beq lw $t 4, $t 6, 0($t 0) $t 4, 1 $zero, Il 0($t 1) #poll recv ready bit lw andi beq sw $t 4, $t 6, 0($t 2) $t 4, 1 zero, I 2 0($t 3) #poll trans ready bit #loop til recv ready #read input character #loop til trans ready #echo (print) character Irwini Fall 2007 PSU

The Downsides of Polling q Input and output devices are very slow compared to the processor l l These time lags are simulated in SPIM which measures time in instructions executed, not in real clock time After the transmitter starts to write a character, the transmitter’s ready bit becomes 0. It doesn’t become ready again until the processor has executed a (large) fixed number of instructions. (You don’t want to single step the simulator!) q Polling will execute the “loop til ready” code thousands of times. While the input or output is occurring, nothing else can be done – a waste of resources. q There is a better way CSE 331 W 13. 14 Irwini Fall 2007 PSU

I/O Interrupts q An I/O interrupt is used to signal an I/O request for service l l Can have different urgencies (so may need to be prioritized) Need to identity the device generating the interrupt q An I/O interrupt is asynchronous wrt instr execution l An I/O interrupt is not associated with any instruction and does not prevent any instruction from completion - You can pick your own convenient point to take an interrupt q Advantage l User program progress is only halted during the actual transfer of I/O data to/from user memory space q Disadvantage l l – special hardware is needed to Cause an interrupt (I/O device) Detect an interrupt and save the proper information to resume after servicing the interrupt (processor) CSE 331 W 13. 15 Irwini Fall 2007 PSU

Interrupt Driven Input Processor 1. input interrupt 2. 1 save PC Memory add sub and or beq user program Receiver Keyboard 2. 2 jump to interrupt service routine 2. 4 return to user code lbu sb. . . jr 2. 3 service interrupt input interrupt service routine memory CSE 331 W 13. 17 Irwini Fall 2007 PSU

Interrupt Driven Input in SPIM 1. the Receiver indicates with an interrupt that it has input a new character from the keyboard into received byte the Receiver data register Receiver data (0 xffff 0004) unused 65 - writing to the Receiver data register sets the Receiver control register ready bit to 1 Receiver control (0 xffff 0000) unused 1 1 0 interrupt enable 2. ready the user process responds to the interrupt by transferring control to an interrupt service routine that copies the input character into the user memory space - reading the Receiver data register resets the Receiver control register ready bit to 0 CSE 331 W 13. 18 Irwini Fall 2007 PSU

Interrupt Driven Output 1. output interrupt Processor 2. 1 save PC Memory Trnsmttr 2. 2 jump to interrupt service routine Display 2. 4 return to user code add sub and or beq lbu sb. . . jr user program 2. 3 service interrupt output interrupt service routine memory CSE 331 W 13. 20 Irwini Fall 2007 PSU

Interrupt Driven Output in SPIM 1. the transmitter indicates with an interrupt that it has successfully output the character in the Transmitter data register in memory to the display transmitted byte Transmitter data (0 xffff 000 c) unused 65 - reading from the Transmitter data register sets the Transmitter control register ready bit to 1 Transmitter control (0 xffff 0008) unused 1 1 0 interrupt enable 2. ready the user process responds to the interrupt by transferring control to an interrupt service routine that writes the next character to output from the user memory space into the Transmitter data register - writing to the Transmitter data register resets the Transmitter control register ready bit to 0 CSE 331 W 13. 21 Irwini Fall 2007 PSU

Additions to MIPS ISA for I/O q Coprocessor 0 records the information the software needs to handle exceptions (including interrupts) l l EPC (register 14) – holds the address+4 of the instruction that was executing when the exception occurred Status (register 12) – exception mask and enable bits 15 8 4 1 0 Intr Mask User mode Intr enable Excp level - Intr Mask = 1 bit for each of 6 hw and 2 sw exception levels (1 enables exception at that level, 0 disables them) - User mode = 0 if running in kernel mode when exception occurred; 1 if running in user mode (fixed at 1 in SPIM) - Excp level = set to 1 (disable exceptions) when an exception occurs; should be reset by exception handler when done - Intr enable = 1 if exception are enabled; 0 if disabled CSE 331 W 13. 22 Irwini Fall 2007 PSU

Additions to MIPS ISA, Con’t l Cause (register 13) – exception pending and type bits 31 Branch delay 15 8 Pending exception (PI) 6 2 Exception code PI 3 = recv intr PI 2 = trans intr - PI: bits set if exception occurs but not yet serviced – so can handle more than one exception occurring at same time, or records exception requests when exception are disabled - Exception code: encodes reasons for exception CSE 331 W 13. 23 – – – – – 0 (INT) external interrupt (I/O device request) 4 (Ad. EL) address error trap (load or instr fetch) 5 (Ad. ES) address error trap (store) 6 (IBE) bus error on instruction fetch trap 7 (DBE) bus error on data load or store trap 8 (Sys) syscall trap 9 (Bp) breakpoint trap 10 (RI) reserved (or undefined) instruction trap 12 (Ov) arithmetic overflow trap Irwini Fall 2007 PSU

MIPS Exception Return Instruction q Exception return – sets the Excp level bit in coprocessor 0’s Status register to 0 (reenabling exception) and returns to the instruction pointed to by coprocessor 0’s EPC register eret 0 x 10 CSE 331 W 13. 24 #return from exception 1 0 0 x 18 Irwini Fall 2007 PSU

Example I/O Interrupts in SPIM - Enable li li mfc 0 andi interrupt mtc 0 $t 0, $t 1, $t 2, $t 3, 0 xffff 0000 0 xffff 0004 0 xffff 0008 0 xffff 000 c #recv ctrl #recv data #trans ctrl #trans data $t 4, $13 $t 4, 0 xffff 00 ff #clear Pending $t 4, $13 #(PI) bits in Cause reg li sw sw $t 4, 0 x 2 $t 4, 0($t 0) $t 4, 0($t 2) #enable recv interrupts #enable trans interrupts mfc 0 ori mtc 0 $t 4, $12 $t 4, 0 xff 01 $t 4, $12 #enable intr and mask #in Status reg #do something useful while I/O is taking place #when I/O interrupts occur transfer control to #exception handler (at address 0 x 80000180) CSE 331 W 13. 25 Irwini Fall 2007 PSU

Example I/O Interrupts in SPIM - Handler. ktext mfc 0 srl andi bne ck_recv: andi beq intr I 1: lw andi beq lw andi Cause reg mtc 0 CSE 331 W 13. 26 0 x 80000180 $t 4, $13 $t 5, $t 4, 2 $t 5, 0 x 1 f $t 5, $zero, excp #get Excp. Code from Cause #Excp. Code in $t 5, if 0 #then I/O intr has occurred $t 5, $t 4, 0 x 800 #check for PI 3 (input), $t 5, $zero, ck_trans #if 0, then trans $t 5, $t 6, $t 4, 0($t 0) #check recv ready $t 5, 1 $zero, no_recv_ready 0($t 1) #input character into $t 6 $t 4, 0 xfffff 7 ff #clear PI 3 bit in $t 4, $13 Irwini Fall 2007 PSU

Example I/O Interrupts in SPIM – Handler, con’t ck_trans: beq echo yet andi beq intr I 2: lw andi beq sw mfc 0 andi Cause reg mtc 0 ret_hand: mfc 0 ori mtc 0 CSE 331 W 13. 27 eret $t 1, $zero, ret_hand #no character to $t 5, $t 4, 0 x 400 #check for PI 2 (output) $t 5, $zero, ret_hand #if 0, then no trans $t 5, $t 6, $t 4, 0($t 2) #check trans ready $t 5, 1 $zero, no_trans_ready 0($t 3) #echo character to display $13 $t 4, 0 xfffffbff #clear PI 2 bit in $t 4, $13 $t 4, $12 $t 4, 0 xff 01 $t 4, $12 #enable intr and mask #in Status reg Irwini #return from intr Fall 2007 PSU

“… designed the P 6 frontside bus to be transactionoriented. Chips that connected to the bus were known as bus agents … This transaction orientation is [now] a standard feature of most modern microprocessor buses, despite its complexity and the implication that all bus agents must continuously monitor the bus and track the overall state … it’s a good trade-off between the expense (wires, motherboard routing, and CPU package pins) and inexpensive (transistors on the CPU) The Pentium Chronicles, Colwell, pg. 76 CSE 331 W 13. 29 Irwini Fall 2007 PSU

Exceptions in General user program normal control flow: sequential, jumps, branches, calls, returns q Exception l Exception System Exception Handler return from exception = unprogrammed control transfer system takes action to handle the exception - must record the address of the offending or next to execute instruction and save (and restore) user state l CSE 331 W 13. 30 returns control to user after handling the exception Irwini Fall 2007 PSU

Two Types of Exceptions q Interrupts l l caused by external events (i. e. , request from I/O device) asynchronous to program execution may be handled between instructions simply suspend and resume user program q Traps l caused by internal events - exceptional conditions (e. g. , arithmetic overflow, undefined instr. ) - errors (e. g. , hardware malfunction, memory parity error) - faults (e. g. , non-resident page – page fault) l l l synchronous to program execution condition must be remedied by the trap handler instruction may be retried (or simulated) and program continued or program may be aborted CSE 331 W 13. 31 Irwini Fall 2007 PSU

Additions to MIPS ISA for Interrupts q Control signals to write EPC (EPCWrite), Cause and Status (Cause&Status. Write) q Hardware to record the type of interrupt in Cause q Modify the finite state machine so that l l the address of interrupt handler (8000 0180 hex) can be loaded into the PC, so must increase the size of PC mux and save the address of the next instr in EPC CSE 331 W 13. 32 Irwini Fall 2007 PSU

Interrupt Modified Multicycle Datapath Interrupt EPCWrite 0 Memory 1 Write Data IR Read Addr 1 Register Read Addr 2 Data 1 File Write Addr Read Data (Instr. or Data) 0 MDR Write Data Shift left 2 EPC 3 2 0 1 zero ALU 4 0 Instr[15 -0] Sign Extend 32 Instr[5 -0] CSE 331 W 13. 34 Data 2 8000 0180 Shift left 2 Instr[25 -0] 1 1 Address PC[31 -28] ALUout PC Instr[31 -26] Cause Status Mem. Read Mem. Write Memto. Reg IRWrite PCSource ALUOp Control ALUSrc. B ALUSrc. A Reg. Write Reg. Dst A Ior. D Cause&Status. Write B PCWrite. Cond PCWrite 0 1 2 3 ALU control Irwini Fall 2007 PSU

Interrupt Modified FSM Decode Ior. D = 0 Instr Fetch 1 Mem. Read; IRWrite ALUSrc. A = 0 Start ALUSrc. B = 11 ALUsrc. B = 01 ALUOp = 00 PCSource = 00 PCWrite pe) q) R-ty be ) sw = = (Op = j) lw or (Op Op Op = ( ( 6 8 9 0 2 ALUSrc. A = 1 ALUSrc. B = 10 ALUOp = 00 (Op = lw) 3 Execute (Op = s w) Memory Access Mem. Read Ior. D = 1 ALUSrc. A = 1 ALUSrc. B = 00 ALUOp = 10 5 Mem. Write Ior. D = 1 ALUSrc. A = 1 ALUSrc. B = 00 ALUOp = 01 PCSource = 01 PCWrite. Cond PCSource = 10 PCWrite 7 Reg. Dst = 1 Reg. Write Memto. Reg = 0 4 11 Reg. Dst = 0 Reg. Write Memto. Reg = 1 Cause&Status. Write EPCWrite; PCWrite Intr. Or. Excp = 0 PCSource = 11 CSE 331 W 13. 36 Write Back Interrupt pending? Irwini Fall 2007 PSU

Additions to MIPS ISA for Traps q Control signals to write EPC (EPCWrite & Intr. Or. Excp), Cause and Status (Cause&Status. Write) q Hardware to record the type of trap in Cause q Further modify the finite state machine so that l for traps, record the address of the current (offending) instruction in the EPC, so must undo the PC = PC + 4 done during fetch CSE 331 W 13. 37 Irwini Fall 2007 PSU

Trap Modified Multicycle Datapath Trap EPCWrite PCSource ALUOp Control ALUSrc. B ALUSrc. A Reg. Write Reg. Dst Memory Read Addr 1 Register Read Addr 2 Data 1 File Write Addr Read 1 Write Data IR Read Data (Instr. or Data) 0 MDR Write Data 2 Shift left 2 EPC 8000 0180 Shift left 2 3 2 0 1 zero ALU 4 0 Instr[15 -0] Sign Extend 32 Instr[5 -0] CSE 331 W 13. 39 PC[31 -28] Instr[25 -0] 1 1 Address 1 0 1 2 3 ALUout PC Instr[31 -26] 0 0 Cause Status Mem. Read Mem. Write Memto. Reg IRWrite Intr. Or. Excp A Ior. D Cause. Write B PCWrite. Cond PCWrite 01 ALU control Irwini Fall 2007 PSU

How Control Detects Two Traps q Undefined instruction (RI) – detected when no next state is defined in state 1 (decode) for the opcode value l Define the next state value for all undefined op values as new state 10 q Arithmetic overflow (Ov) – The overflow signal from the ALU is used in state 6 (if don’t want to complete Reg. Write) q Need to modify the FSM in a similar fashion for remaining traps l Challenge is to handle the interactions between instructions and exception-causing events so that the control logic remains small and fast - Complex interactions makes the control unit the most challenging aspect of hardware design, especially in pipelined processors CSE 331 W 13. 40 Irwini Fall 2007 PSU

Trap Modified FSM Decode Ior. D = 0 Instr Fetch 1 Mem. Read; IRWrite ALUSrc. A = 0 Start ALUSrc. B = 11 ALUsrc. B = 01 ALUOp = 00 PCSource = 00 PCWrite pe) q) R-ty be ) sw = = (Op = j) lw or (Op Op Op = ( ( 6 8 9 0 p (O = ALUSrc. A = 1 ALUSrc. B = 10 ALUOp = 00 (Op = lw) 3 Execute (Op = s w) Memory Access Mem. Read Ior. D = 1 CSE 331 W 13. 42 5 Mem. Write Ior. D = 1 4 Reg. Dst = 0 Reg. Write Memto. Reg = 1 ALUSrc. A = 1 ALUSrc. B = 00 ALUOp = 10 Write Back ALUSrc. A = 1 ALUSrc. B = 00 ALUOp = 01 PCSource = 01 PCWrite. Cond ) r he ot 2 PCSource = 10 PCWrite No Overflow 7 Reg. Dst = 1 Reg. Write Memto. Reg = 0 10 Cause&Status. Write ALUSrc. A =0 Overflow ALUSrc. B = 01 ALUOp = 01 EPCWrite; PCWrite Intr. Or. Excp = 1 11 Interrupt. PCSource = 11 pending? Cause&Status. Write EPCWrite; PCWrite Intr. Or. Excp = 0 PCSource = 11 Irwini Fall 2007 PSU

I/O System Interconnect Issues interrupt signals Processor Cache Memory bus Memory - I/O Bus Main Memory I/O Controller Disk I/O Controller Terminal I/O Controller Network q Usually have more than one I/O device in the system connected to the processor via a bus l CSE 331 W 13. 44 each I/O device is controlled by an I/O Controller Irwini Fall 2007 PSU

Buses q. A bus is a shared communication link (a single set of wires used to connect multiple subsystems) that needs to support a range of devices with widely varying latencies and data transfer rates l Advantages - Versatile – new devices can be added easily and can be moved between computer systems that use the same bus standard - Low cost – a single set of wires is shared in multiple ways l Disadvantages - Creates a communication bottleneck – bus bandwidth limits the maximum I/O throughput q The l l maximum bus speed is largely limited by The length of the bus The number of devices on the bus CSE 331 W 13. 45 Irwini Fall 2007 PSU

I/O Performance Measures q I/O bandwidth (throughput) – amount of information that can be input (output) and communicated across an interconnect (e. g. , a bus) to the processor/memory (I/O device) per unit time 1. 2. q I/O response time (latency) – the total elapsed time to accomplish an input or output operation l q How much data can we move through the system in a certain time? How many I/O operations can we do per unit time? An especially important performance metric in real-time systems Many applications require both high throughput and short response times CSE 331 W 13. 46 Irwini Fall 2007 PSU

Types of Buses q Processor-memory l l l bus (proprietary) Short and high speed Matched to the memory system to maximize the memoryprocessor bandwidth Optimized for cache block transfers q Backplane bus (industry standard, e. g. , ATA, PCIexpress) l l q I/O l l l The backplane is an interconnection structure within the chassis Used as an intermediary bus connecting I/O busses to the processor-memory bus (industry standard, e. g. , SCSI, USB, Firewire) Usually is lengthy and slower Needs to accommodate a wide range of I/O devices Connects to the processor-memory bus or backplane bus CSE 331 W 13. 47 Irwini Fall 2007 PSU

Example: The Pentium 4’s Buses Memory Controller Hub (“Northbridge”) Graphics output: 2. 0 GB/s Gbit ethernet: 0. 266 GB/s 2 serial ATAs: 150 MB/s 2 parallel ATA: 100 MB/s System Bus (“Front Side Bus”): 64 b x 800 MHz (6. 4 GB/s), 533 MHz, or 400 MHz DDR SDRAM Main Memory Hub Bus: 8 b x 266 MHz PCI: 32 b x 33 MHz 8 USBs: 60 MB/s I/O Controller Hub (“Southbridge”) CSE 331 W 13. 48 Irwini Fall 2007 PSU

Bus Bandwidth Determinates q The bandwidth of a bus is determined by Whether its is synchronous or asynchronous and the timing characteristics of the protocol used l The bus width (i. e. , number of data lines) l Whether the bus supports block transfers or only word at a time transfers l Firewire Type Data lines Clocking Max # devices Max length Peak bandwidth CSE 331 W 13. 49 I/O 4 Asynchronous 63 4. 5 meters 50 MB/s (400 Mbps) 100 MB/s (800 Mbps) USB 2. 0 I/O 2 Synchronous 127 5 meters 0. 2 MB/s (low) 1. 5 MB/s (full) 60 MB/s (high) Irwini Fall 2007 PSU

Buses in Transition q Companies are transitioning from synchronous, parallel, wide buses to asynchronous narrow buses l Reflection on wires and clock skew makes it difficult to use 16 to 64 parallel wires running at a high clock rate (e. g. , ~400 MHz) so companies are transitioning to buses with a few one-way wires running at a very high “clock” rate (~2 GHz) Total # wires # data wires Clock (MHz) Peak BW (MB/s) CSE 331 W 13. 50 PCI 120 32 – 64 (2 -way) 33 – 133 128 – 1064 PCIexpress 36 2 x 4 (1 -way) 635 300 ATA 80 16 (2 -way) 50 100 Serial ATA 7 2 x 2 (1 -way) 150 375 (3 Gbps) Irwini Fall 2007 PSU

ATA Cable Sizes q Serial ATA cables (red) are much thinner than parallel ATA cables (green) CSE 331 W 13. 51 Irwini Fall 2007 PSU