CSC 4250 Computer Architectures September 26 2006 Appendix

CSC 4250 Computer Architectures September 26, 2006 Appendix A. Pipelining

Checks before Instruction Issue n n Check for structural hazards ─ FP divide, register write port Check for RAW hazard ─ check if source registers of instruction in ID is listed as a destination in ID/A 1, A 1/A 2, A 2/A 3, ID/M 1, M 1/M 2, M 2/M 3, …, M 5/M 6, D Check for WAW hazard ─ check if instruction in ID has the same register destination as any instruction in A 1, …, A 4, M 1, …, M 7, D Have we forgotten about WAR hazard?

Example on why no WAR hazards n Modify Figure A. 33: 1. 2. 3. 4. L. D MUL. D ADD. D S. D F 4, O(R 2) F 0, F 4, F 6 F 4, F 0, F 8 F 4, O(R 2) Clock cycle Number In. 1 2 3 4 5 6 1. IF ID EX ME WB 2. IF 3. IF 4. IF 7 8 9 10 11 12 13 14 15 16 17 Fill in the blanks

How Imprecise Exception May Arise n Consider code: DIV. D ADD. D SUB. D n n F 0, F 2, F 4 F 10, F 8 F 12, F 14 Will get out-of-order completion Suppose SUB. D causes a FP exception after ADD. D completes (but before DIV. D finishes) Next, DIV. D causes a FP exception Cannot restore the state to before DIV. D, as ADD. D has destroyed one of its operands

Performance of MIPS FP Pipeline n n The MIPS FP pipeline generates both structural stalls for the divide unit and stalls for RAW hazards (it can also have WAW hazards, but this rarely occurs in practice). Figure A. 35 shows the number of stall cycles for each type of FP operation. The stall cycles per operation track the latency of the FP operations, varying from 46% to 59% of the latency of the FU.

Fig. A. 35. Stalls per FP operation for FP SPEC 89

Stalls for SPEC 89 FP Benchmarks n n Consider data in Figure A. 35 Except for the divide structural hazards, these data do not depend on the frequency of an operation, only on its latency and the # of cycles before the result is used The number of stalls from RAW hazards roughly tracks the latency of the FP unit. For example, the average number of stalls per FP add, subtract, or convert is 1. 7 cycles, or 56% of the latency (3 cycles). Likewise, the average number of stalls for multiplies and divides are 2. 8 and 14. 2, resp. , or 46% and 59% of the corr. latency Structural hazards for divides are rare, since the divide frequency is low

Fig. A. 36. Stalls per instr. for FP SPEC 89

MIPS R 4000 Pipeline n n Implements MIPS 64 but uses a deeper pipeline Achieve higher clock rates by decomposing fivestage integer pipeline into eight stages Extra pipeline stages from decomposing memory access Sometimes called superpipelining

Eight-stage Pipeline Structure of R 4000 n It uses pipelined instruction and data caches

Functions of the Eight Stages (1) 1. IF ─ q q q 2. IS ─ q q 3. Second half of instruction fetch Complete instruction cache access RF ─ q q q 4. First half of instruction fetch PC selection Initiation of instruction cache access Instruction decode and register fetch Hazard check Instruction cache hit detection EX ─ q Execution (including effective address calculation, ALU operation, branch-target calc. and condition evaluation. )

Functions of the Eight Stages (2) 5. DF 6. DS 7. TC 8. WB ─ Data fetch, 1 st half of data cache access ─ 2 nd half of data fetch, Complete data cache access ─ Tag check, Determine if data cache access is hit ─ Write back for loads and RR operations

Two-cycle Load Delay for R 4000

Example of Load 2 -cycle Stall Clock number Instruction no. LD R 1, … DADD R 2, R 1, … DSUB R 3, R 1, … OR R 4, R 1 1 IF 2 IS IF 3 RF IS IF 4 EX RF IS IF 5 DF st st st 6 DS st st st 7 TC EX RF IS 8 WB DF EX RF 9 DS DF EX

Three-cycle Branch Delay for R 4000 § Evaluate branch condition during EX

Example of Taken Branch Clock number Instruction no. 1 2 3 4 5 Branch instruction Delay slot Stall Branch instruction IF IS IF RF IS st EX RF st st DF EX st st IF 6 7 8 DS TC WB DF DS TC st st st IS RF EX 9 WB st st DF

Example of Untaken Branch Instruction no. 1 Branch instruction Delay slot Branch instruction+2 Branch instruction+3 IF n n Clock number 2 3 4 IS IF RF IS IF EX RF IS IF 5 6 DF EX RF IS DS DF EX RF 7 8 TC WB DS TC DF DS EX DF 9 WB TC DS R 4000 uses a predicted-not-taken strategy for the remaining two cycles of the branch delay. Advantage over predicted-taken strategy?

R 4000 FP Pipeline FP instruction Latency Initiation interval Add, subtract 4 3 Multiply 8 4 Divide 36 35 Square root 112 111 Negate 2 1 Absolute value 2 1 FP compare 3 2

Major Causes of R 4000 Pipeline Stalls n n n Load stalls ─ use of a load result 1 or 2 cycles after the load Branch stalls ─ 2 -cycle stall on taken branch plus unfilled or cancelled branch delay slots FP result stalls ─ RAW hazards for operand FP structural stalls ─ conflicts for func. units WAW stalls are not common

Pipeline CPI for 10 SPEC 92 Benchmarks n The pipeline CPI varies from 1. 2 to 2. 8. The left five programs are integer programs, and branch delays are the major CPI contributor. The right five programs are FP, and FP result stalls are the major contributors.

Pipeline CPI and Major Sources of Stalls Benchmark CPI Load Branch Result Structure Gcc 1. 56 0. 13 0. 43 0. 00 Int. average 1. 54 0. 16 0. 38 0. 00 Hydro 2 d 2. 53 0. 00 0. 62 0. 75 0. 17 FP average 2. 48 0. 01 0. 33 0. 95 0. 18 Overall average 2. 00 0. 10 0. 36 0. 46 0. 09

MIPS R 4300 Pipeline n n n n Manufactured by NEC 64 bit processor implements MIPS 64 IS Embedded applications Nintendo-64 game processor High-end color laser printer Multiple EX stages for FP operations Instructions complete out of order FP instruction generates exception after a following integer instruction has completed, leading to an imprecise exception