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CPE/EE 421 Microcomputers: Motorola 68000 – The CPU Hardware Model Instructor: Dr Aleksandar Milenkovic CPE/EE 421 Microcomputers: Motorola 68000 – The CPU Hardware Model Instructor: Dr Aleksandar Milenkovic Lecture Notes CPE/EE 421/521 Microcomputers

Outline n n n 68000 interface Timing diagram Minimal configuration using the 68000 Extensions Outline n n n 68000 interface Timing diagram Minimal configuration using the 68000 Extensions Exception Processing CPE/EE 421/521 Microcomputers 2

68000 Interface n M 68000: 64 pins, arranged in 9 groups: n Address Bus: 68000 Interface n M 68000: 64 pins, arranged in 9 groups: n Address Bus: A 01 – A 23 Data Bus: D 00 – D 15 Asynchronous bus control: AS*, R/W*, UDS*, LDS*, DTACK*, BERR* Synchronous bus control: E, VPA*, VMA* Bus arbitration control: BR*, BGACK* Function code: FC 0, FC 1, FC 2 System control: CLK, RESET*, HALT* Interrupt control: IPL 0*, IPL 1*, IPL 2* Miscellaneous: Vcc(2), Gnd(2) n Legend: Type n n n XX XX XX Input Output Input/Output CPE/EE 421/521 Microcomputers 3

68000 Interface, cont’d n Classification of pins based on function n SYSTEM SUPPORT PINS 68000 Interface, cont’d n Classification of pins based on function n SYSTEM SUPPORT PINS n n MEMORY AND PERIPHERAL INTERFACE PINS n n Connect the processor to an external memory subsystem SPECIAL-PURPOSE PINS (not needed in a minimal application of the processor) n n Essential in every 68000 system (power supply, clock, …) Provide functions beyond basic system functions Terminology n n n Asterisk following a name: indicates the signal is active low “Signal is asserted” means signal is placed in its active state “Signal is negated” means signal is placed in its inactive state CPE/EE 421/521 Microcomputers 4

System Support Pins n Power Supply n n Clock n n Single +5 V System Support Pins n Power Supply n n Clock n n Single +5 V power supply: 2 Vcc pins and 2 ground pins Single-phase, TTL-compatible signal Bus cycle: memory access, consists of a minimum 4 clock cycles Instruction: consists of one or more bus cycles RESET* n Forces the 68000 into a known state on the initial application of power: n n supervisor’s A 7 is loaded from memory location $00 0000 Program counter is loaded from address $00 0004 During power-up sequence must be asserted together with the HALT* input for at least 100 ms. Acts also as an output, when processor executes the instruction RESET (used to reset peripherals w/out resetting the 68000) CPE/EE 421/521 Microcomputers 5

System Support Pins, cont’d n HALT* n n In simple 68000 systems can be System Support Pins, cont’d n HALT* n n In simple 68000 systems can be connected together with RESET* Can be used: n n by external devices to make the 68000 stop execution after current bus cycle (and to negate all control signals) to single-step (bus cycle by bus cycle) through program to rerun a failed bus cycle (if memory fails to respond correctly) in conjunction with the bus error pin, BERR* It can be used as an output, to indicate that the 68000 found itself in situation from which it cannot recover (HALT* is asserted) CPE/EE 421/521 Microcomputers 6

Memory and Peripheral Interface Pins n Address Bus n n n 23 -bit address Memory and Peripheral Interface Pins n Address Bus n n n 23 -bit address bus, permits 223 16 -bit words to be addressed Tri-state output pins (to permit devices other then the CPU to take a control over it) Auxiliary function: n n supports vectored interrupts Address lines A 01, A 02, A 03 indicate the level of the interrupt being serviced All other address lines are set to a high level Data Bus n Bi-directional 16 -bit wide data bus n n During a CPU read cycle acts as an input During a CPU write cycle acts as an output Byte operations: only D 00 -D 07 or D 08 -D 15 are active Interrupting device identifies itself to the CPU by placing an interrupt vector number on D 00 -D 07 during an interrupt acknowledge cycle CPE/EE 421/521 Microcomputers 7

Memory and Peripheral Interface Pins, cont’d n AS* n n When asserted, indicates that Memory and Peripheral Interface Pins, cont’d n AS* n n When asserted, indicates that the content of the address bus is valid. R/W* n Determines the type of a memory access cycle n n n CPU is reading from memory: R/W* = 1 CPU is writing to memory: R/W* = 0 If CPU is performing internal operation, R/W* is always 1 When CPU relinquishes control of its busses, R/W* is undefined UDS* and LDS* n n n Used to determine the size of the data being accessed If both UDS* and LDS* are asserted, word is accessed R/W* UDS* LDS* n n n 010: write lower byte (D 00 – D 07: data valid, replicated on D 8 -D 15) 000: write word (D 00 – D 15: data valid) 101: read upper byte (D 00 – D 07: invalid, D 8 -D 15 – data valid) CPE/EE 421/521 Microcomputers 8

Memory and Peripheral Interface Pins, cont’d n DTACK* (Data Transfer Acknowledge) n n n Memory and Peripheral Interface Pins, cont’d n DTACK* (Data Transfer Acknowledge) n n n Handshake signal generated by the device being accessed Indicates that the contents of the data bus is valid If DTACK* is not asserted, CPU generates waitstates until DTACK goes low or until an error state is declared. When DTACK* is asserted, CPU completes the current access and begins the next cycle DTACK* has to be generated a certain time after the beginning of a valid memory access (timer supplied by the system designer). CPE/EE 421/521 Microcomputers 9

Memory and Peripheral Interface Pins, cont’d Figure 4. 3 CPE/EE 421/521 Microcomputers 10 Memory and Peripheral Interface Pins, cont’d Figure 4. 3 CPE/EE 421/521 Microcomputers 10

Special-Function Pins of the 68000 n BERR* n n (Bus Arbitration Control) Used to Special-Function Pins of the 68000 n BERR* n n (Bus Arbitration Control) Used to implement multiprocessor systems based on M 68000 FC 0 -FC 2 (Function Code Output) n n n Enables the 68000 to recover from errors within the memory system BR*, BGACK* n n (Bus Error Control) Indicate the type of cycle currently being executed Becomes valid approximately half a clock cycle earlier than the contents of the address bus IPL 0*-IPL 2* n n (Interrupt Control Interface) Used by an external device to indicate that it requires service 3 -bit code specifies one of eight levels of interrupt request CPE/EE 421/521 Microcomputers 11

Special-Function Pins of the 68000 Function Code Outputs CPE/EE 421/521 Microcomputers 12 Special-Function Pins of the 68000 Function Code Outputs CPE/EE 421/521 Microcomputers 12

Special-Function Pins of the 68000 Using FC Outputs User data memory User program memory Special-Function Pins of the 68000 Using FC Outputs User data memory User program memory Supervisor program and data memory Figure 4. 8 CPE/EE 421/521 Microcomputers 13

Special-Function Pins of the 68000 Asynchronous Bus Control Figure 4. 11 n The 68000 Special-Function Pins of the 68000 Asynchronous Bus Control Figure 4. 11 n The 68000 is not fully asynchronous because its actions are synchronized with a clock input n It can prolong a memory access until an ACK is received, but it has to be in increments of one clock cycle CPE/EE 421/521 Microcomputers 14

Outline n n n 68000 interface Timing diagram Minimal configuration using the 68000 Extensions Outline n n n 68000 interface Timing diagram Minimal configuration using the 68000 Extensions Exception Processing CPE/EE 421/521 Microcomputers 15

Timing Diagram of a Simple Flip-Flop Idealized form of the timing diagram Actual behavior Timing Diagram of a Simple Flip-Flop Idealized form of the timing diagram Actual behavior of a D flip-flop Data hold time Data setup time Max time for output to become valid after clock CPE/EE 421/521 Microcomputers 16

General form of the timing diagram An alternative form of the timing diagram CPE/EE General form of the timing diagram An alternative form of the timing diagram CPE/EE 421/521 Microcomputers 17

The Clock n n A microprocessor requires a clock that provides a stream of The Clock n n A microprocessor requires a clock that provides a stream of timing pulses to control its internal operations A 68000 memory access takes a minimum of eight clock states numbered from clock state S 0 to clock state S 7 CPE/EE 421/521 Microcomputers 18

Bus Cycle A memory access begins in clock state S 0 and ends in Bus Cycle A memory access begins in clock state S 0 and ends in state S 7 CPE/EE 421/521 Microcomputers 19

Bus Cycle The most important parameter of the clock is the duration of a Bus Cycle The most important parameter of the clock is the duration of a cycle, t. CYC. CPE/EE 421/521 Microcomputers 20

Bus Cycle At the start of a memory access the CPU sends the address Bus Cycle At the start of a memory access the CPU sends the address of the location it wishes to read to the memory CPE/EE 421/521 Microcomputers 21

Address Timing n n We are interested in when the 68000 generates a new Address Timing n n We are interested in when the 68000 generates a new address for use in the current memory access The next slide shows the relationship between the new address and the state of the 68000’s clock CPE/EE 421/521 Microcomputers 22

Bus Cycle In state S 1 a new Initially, in state address becomes S Bus Cycle In state S 1 a new Initially, in state address becomes S 0 the address valid for the remainder bus contains the of the memory access old address CPE/EE 421/521 Microcomputers 23

Bus Cycle The time at which the contents of the address bus change can Bus Cycle The time at which the contents of the address bus change can be related to the edges of the clock. CPE/EE 421/521 Microcomputers 24

Address Timing n n n Let’s look at the sequence of events that govern Address Timing n n n Let’s look at the sequence of events that govern the timing of the address bus The “old” address is removed in state S 0 The address bus is floated for a short time, and the CPU puts out a new address in state S 1 CPE/EE 421/521 Microcomputers 25

Bus Cycle The old address is removed in clock state S 0 and the Bus Cycle The old address is removed in clock state S 0 and the address bus floated CPE/EE 421/521 Microcomputers 26

Bus Cycle t. CLAV The designer is interested in the point at which the Bus Cycle t. CLAV The designer is interested in the point at which the address first becomes valid. This point is t. CLAV seconds after the falling edge of S 0. CPE/EE 421/521 Microcomputers 27

Bus Cycle The memory needs to know when the address from the CPU is Bus Cycle The memory needs to know when the address from the CPU is valid. An address strobe, AS*, is asserted to indicate that the address is valid. CPE/EE 421/521 Microcomputers 28

Address and Address Strobe n n n We are interested in the relationship between Address and Address Strobe n n n We are interested in the relationship between the time at which the address is valid and the time at which the address strobe, AS*, is asserted When AS* is active-low it indicates that the address is valid We now look at the timing of the clock, the address, and the address strobe CPE/EE 421/521 Microcomputers 29

Bus Cycle AS* goes active low after the address has become valid AS* goes Bus Cycle AS* goes active low after the address has become valid AS* goes inactive high before the address changes CPE/EE 421/521 Microcomputers 30

Bus Cycle AS* goes low in clock state S 2 CPE/EE 421/521 Microcomputers 31 Bus Cycle AS* goes low in clock state S 2 CPE/EE 421/521 Microcomputers 31

The Data Strobes n n n The 68000 has two data strobes LDS* and The Data Strobes n n n The 68000 has two data strobes LDS* and UDS*. These select the lower byte or the upper byte of a word during a memory access To keep things simple, we will use a single data strobe, DS* The timing of DS* in a read cycle is the same as the address strobe, AS* CPE/EE 421/521 Microcomputers 32

Bus Cycle The data strobe, is asserted at the same time as AS* CPE/EE Bus Cycle The data strobe, is asserted at the same time as AS* CPE/EE 421/521 Microcomputers in a read cycle 33

The Data Bus n n n During a read cycle the memory provides the The Data Bus n n n During a read cycle the memory provides the CPU with data The next slide shows the data bus and the timing of the data signal Note that valid data does not appear on the data bus until near the end of the read cycle CPE/EE 421/521 Microcomputers 34

Bus Cycle Data from the memory appears near the end of the read cycle Bus Cycle Data from the memory appears near the end of the read cycle CPE/EE 421/521 Microcomputers 35

Analyzing the Timing Diagram n n We are going to redraw the timing diagram Analyzing the Timing Diagram n n We are going to redraw the timing diagram to remove clutter We aren’t interested in the signal paths themselves, only in the relationship between the signals CPE/EE 421/521 Microcomputers 36

Bus Cycle We are interested in the relationship between the clock, AS*/DS* and the Bus Cycle We are interested in the relationship between the clock, AS*/DS* and the data in a read cycle CPE/EE 421/521 Microcomputers 37

Bus Cycle The earliest time at which the memory can begin to access data Bus Cycle The earliest time at which the memory can begin to access data is measured from the point at which the address is first valid CPE/EE 421/521 Microcomputers 38

Bus Cycle Data becomes valid Address becomes valid The time between address valid and Bus Cycle Data becomes valid Address becomes valid The time between address valid and data valid is the memory’s CPE/EE 421/521 Microcomputers access time, tacc 39

Calculating the Access Time n n n We need to calculate the memory’s access Calculating the Access Time n n n We need to calculate the memory’s access time By knowing the access time, we can use the appropriate memory component Equally, if we select a given memory component, we can calculate whether its access time is adequate for a particular system CPE/EE 421/521 Microcomputers 40

Bus Cycle Data from the memory is latched into the 68000 by the falling Bus Cycle Data from the memory is latched into the 68000 by the falling edge of the clock CPE/EE 421/521 Microcomputers in state S 6. 41

Bus Cycle Data must be valid t. DICL seconds before the falling CPE/EE 421/521 Bus Cycle Data must be valid t. DICL seconds before the falling CPE/EE 421/521 Microcomputers edge of S 6 42

Bus Cycle We know that the time between the address valid and data valid Bus Cycle We know that the time between the address valid and data valid is tacc CPE/EE 421/521 Microcomputers 43

Bus Cycle The address becomes valid t. CLAV seconds after the falling edge of Bus Cycle The address becomes valid t. CLAV seconds after the falling edge of S 0 CPE/EE 421/521 Microcomputers 44

Bus Cycle From the falling • the address becomes valid edge of S 0 Bus Cycle From the falling • the address becomes valid edge of S 0 to the • the data is accessed CPE/EE 421/521 Microcomputers falling edge of S 6: • the data is captured 45

Bus Cycle The falling edge of S 0 to the falling edge of S Bus Cycle The falling edge of S 0 to the falling edge of S 6 is three clock cycles CPE/EE 421/521 Microcomputers 46

Bus Cycle 3 tcyc = t. CLAV + tacc + t. DICL CPE/EE 421/521 Bus Cycle 3 tcyc = t. CLAV + tacc + t. DICL CPE/EE 421/521 Microcomputers 47

Timing Example n n n n 68000 clock 8 MHz t. CYC = 125 Timing Example n n n n 68000 clock 8 MHz t. CYC = 125 ns 68000 CPU t. CLAV = 70 ns 68000 CPU t. DICL = 15 ns What is the minimum tacc? 3 t. CYC = t. CLAV + tacc + t. DICL 375 = 70 + tacc + 15 tacc = 290 ns CPE/EE 421/521 Microcomputers 48

A 68000 Read Cycle Figure 4. 14 CPE/EE 421/521 Microcomputers 49 A 68000 Read Cycle Figure 4. 14 CPE/EE 421/521 Microcomputers 49

Extended Read Cycle DTACK* did not go low at least 20 ns before the Extended Read Cycle DTACK* did not go low at least 20 ns before the falling edge of state S 4 Figure 4. 15 n Designer has to provide logic to control DTACK* CPE/EE 421/521 Microcomputers 50

Memory Timing Diagram n The 6116 static memory component n n n 2 K Memory Timing Diagram n The 6116 static memory component n n n 2 K x 8 bit memory – byte-oriented! Two 6116’s configured in parallel to allow word accesses Eleven address inputs Figure 4. 18 CPE/EE 421/521 Microcomputers 51

Memory Timing 200 ns – address stable) (min Diagram, cont’d (max 200 ns) (usually Memory Timing 200 ns – address stable) (min Diagram, cont’d (max 200 ns) (usually derived from UDS*/LDS*) Data is floating Figure 4. 17 n Assumptions: n n (max 15 ns) (max 50 ns) R/W* is high for the duration of the read cycle OE* is low CPE/EE 421/521 Microcomputers 52

Connecting The 6116 RAM to a 68000 CPU Inputs Outputs RAMCS D 00 A Connecting The 6116 RAM to a 68000 CPU Inputs Outputs RAMCS D 00 A LDS* CS 1* CS 2* Operation AS* UDS* 01 * 1 X X X 1 1 No operation D 07 X 1 XA X 1 1 No operation 11 0 0 0 Word read 0 0 0 1 Upper byte read 0 0 1 0 Lower byte read 0 0 1 1 No operation D 08 A 01 A 11 A 01 D 15 A 11 A 12 Figure 4. 19 A 23 CPE/EE 421/521 Microcomputers 53

Connecting The 6116 RAM to a 68000 CPU Timing Diagram 70 ns 10 ns Connecting The 6116 RAM to a 68000 CPU Timing Diagram 70 ns 10 ns Turnoff time 70+10+60 = 140 ns 60 ns Figure 4. 20 CPE/EE 421/521 Microcomputers 54

Timing Example n 68000 clock 8 MHz n n n 68000 CPU t. CLAV Timing Example n 68000 clock 8 MHz n n n 68000 CPU t. CLAV = 70 ns 68000 CPU t. DICL = 15 ns What is the minimum tacc? 3 × t. CYC > t. CLAV + tacc + t. DICL 375 > 70 + tacc + 15 tacc < 290 ns (or t. AA from the timing diagram, access time) For the 12. 5 MHz version of 68000 n t. CYC = 125 ns 68000 CPU 3× 80 > 55 + tacc + 10 tacc < 175 ns t. CYC = 80 ns t. CLAV = 55 ns t. DICL = 10 ns Remember, maximum t. AA for the 6116 RAM was 200 ns CPE/EE 421/521 Microcomputers 55

68000 Write Cycle n n 68000 transmits a byte or a word to memory 68000 Write Cycle n n 68000 transmits a byte or a word to memory or a peripheral Essential differences: n n The CPU provides data at the beginning of a write cycle One of the bus slaves (see later) reads the data In a read cycle DS* and AS* were asserted concurrently This will be not a case here! Reason for that: 68000 asserts DS* only when the contents of data bus have stabilized n Therefore, memory can use UDS*/LDS* to latch data from the CPU CPE/EE 421/521 Microcomputers 56

Simplified write cycle timing diagram In a write cycle: UDS*/LDS* is asserted one cycle Simplified write cycle timing diagram In a write cycle: UDS*/LDS* is asserted one cycle after AS* Figure 4. 22 CPE/EE 421/521 Microcomputers 57

Write Cycle n Follow this sequence of events in a write cycle: n n Write Cycle n Follow this sequence of events in a write cycle: n n n Address stable AS* asserted R/W* brought low Data valid DS* asserted CPE/EE 421/521 Microcomputers 58 Figure 4. 23

Write Cycle Timing Diagram of a 6116 RAM Write recovery time (min 10 ns) Write Cycle Timing Diagram of a 6116 RAM Write recovery time (min 10 ns) Address valid to end of write (min 120 ns) Write pulse width (min 90 ns) Address setup time (min 20 ns) CPE/EE 421/521 Microcomputers Figure 4. 24 59

Write Cycle Timing Diagram of a 6116 RAM, cont’d n n n Write cycle Write Cycle Timing Diagram of a 6116 RAM, cont’d n n n Write cycle ends with either CS* or WE* being negated (CS* and WE* internally combined) An address must be valid for at least t. AS nanoseconds before WE* is asserted Must remain valid for at least t. WR nanoseconds after WE* is negated Data from the CPU must be valid for at least t. DW nanoseconds before WE* is negated Must remain valid for at least t. DH nanoseconds after the end of the cycle CPE/EE 421/521 Microcomputers 60

Designing a Memory Subsystem An Example n Design a M 68000 memory subsystem using Designing a Memory Subsystem An Example n Design a M 68000 memory subsystem using n n Two 32 K × 8 RAM chips residing at address $00 8000 Two 8 K × 8 RAM chips residing in the consecutive window LS 138 (3 to 8 decoder) and basic logic gates Solution n n 32 K is 4 × 8 K => Let’s split the address space into 8 K modules In total, we have five (4+1) 8 K windows To address each line in 8 K window => 13 bits (23*210 = 213 = 8 K) To address five modules we need 3 bits Don’t forget that there is no A 0, we will use LDS/UDS CPE/EE 421/521 Microcomputers 61

Designing a Memory Subsystem An Example CPE/EE 421/521 Microcomputers 62 Designing a Memory Subsystem An Example CPE/EE 421/521 Microcomputers 62

Designing a Memory Subsystem An Example CPE/EE 421/521 Microcomputers 63 Designing a Memory Subsystem An Example CPE/EE 421/521 Microcomputers 63

Interrupt Control Interface (details later) low p r i o r i t y Interrupt Control Interface (details later) low p r i o r i t y high Figure 4. 9 CPE/EE 421/521 Microcomputers 64

Bus Arbitration Control n n n When 68000 controls the address and data buses, Bus Arbitration Control n n n When 68000 controls the address and data buses, we call it the bus master The 68000 may allow another 68000 or DMA controller to take control over buses In the system with only one bus master, 68000 would have permanent control of the address and data buses Address bus Data bus Control bus Arbitration bus Slave module Master module CPU Memory I/O Local memory Master module CPU Local memory I/O CPE/EE 421/521 Microcomputers 65

Bus Arbitration Control, cont’d n n 68000 must respond to BR* request (it cannot Bus Arbitration Control, cont’d n n 68000 must respond to BR* request (it cannot be masked) Assertion of BG* indicates that the bus will be given up at the end of present bus cycle Requesting device waits until AS*, DTACK*, and BGACK* have been negated, and only then asserts its own BGACK* output Old master negates its BG*, and BR* can be asserted by another potential master CPE/EE 421/521 Microcomputers 66

Data Bus Contention in Microcomputers n n n Situation where more than one device Data Bus Contention in Microcomputers n n n Situation where more than one device attempts to drive the bus simultaneously Example: Two memory modules, M 1 selected during read cycle 1, M 2 selected during read cycle 2 Assumption: n n M 1 has data bus drivers with relatively long turn-off times M 2 has data bus drivers with relatively short turn-on times Figure 4. 27 a CPE/EE 421/521 Microcomputers 67

Data Bus Contention in Microcomputers, cont’d Long turn-off time Short turn-on time CPE/EE 421/521 Data Bus Contention in Microcomputers, cont’d Long turn-off time Short turn-on time CPE/EE 421/521 Microcomputers 68

Bus Contention and Data Bus Transceivers n n Data bus transceiver – consists of Bus Contention and Data Bus Transceivers n n Data bus transceiver – consists of a transmitter (driver) and a receiver Driver – tristate output, can be driven high, low, or internally disconnected form the rest of the circuit Two control inputs: Enable (active low) and DIR (direction) Dynamic data bus CPE/EE 421/521 Microcomputers contention 69

Outline n n n 68000 interface Timing diagram Minimal configuration using the 68000 Extensions Outline n n n 68000 interface Timing diagram Minimal configuration using the 68000 Extensions Exception Processing CPE/EE 421/521 Microcomputers 70

DESIGN CONSTRAINTS n n n n Used in stand-alone mode Classroom teaching aid 16 DESIGN CONSTRAINTS n n n n Used in stand-alone mode Classroom teaching aid 16 KB EPROM-based monitor Speed is not important At least 4 KB RAM 1 serial and 1 parallel port Memory expandable No interrupts and multiple processors CPE/EE 421/521 Microcomputers 71

MAJOR COMPONENTS n n ROM – Two 8 K × 8 components RAM – MAJOR COMPONENTS n n ROM – Two 8 K × 8 components RAM – Two 2 K × 8 components Parallel – 6821 Peripheral Interface Adapter (PIA) Serial – 6850 Asynchronous Comm. Interface Adapter (ACIA) CPE/EE 421/521 Microcomputers 72

DESIGH CHOICES n Chose the location of ROM (16 KB) and RAM (8 KB) DESIGH CHOICES n Chose the location of ROM (16 KB) and RAM (8 KB) within the address space (16 MB) n n n Unimportant, as long as the reset vectors are located at $00 0000 Chose the location of memory-mapped peripherals Control of DTACK* (is delay applied or not? ) CPE/EE 421/521 Microcomputers 73

The 68000’s Reset Sequence CPE/EE 421/521 Microcomputers 74 The 68000’s Reset Sequence CPE/EE 421/521 Microcomputers 74

REMEMBER n When the RESET* pin is asserted for the appropriate duration: n SR REMEMBER n When the RESET* pin is asserted for the appropriate duration: n SR = $2700 n SSP is loaded with the longword @ $00 0000 n PC is loaded with the longword @ $00 0004 CPE/EE 421/521 Microcomputers 75

Block Diagram of a 68000 based microcomputer Figure 4. 43 CPE/EE 421/521 Microcomputers 76 Block Diagram of a 68000 based microcomputer Figure 4. 43 CPE/EE 421/521 Microcomputers 76

Memory and Peripheral Components n n n We assigned address lines to address pins, Memory and Peripheral Components n n n We assigned address lines to address pins, and data lines to data pins. Before designing logic that will generate chip select signals, we have to decide about RAM/ROM location. To assure that the reset vector location is at $00 0000, let’s situate 16 KB of ROM at $00 0000 CPE/EE 421/521 Microcomputers 77

Memory and Peripheral Components Figure 4. 44 CPE/EE 421/521 Microcomputers 78 Memory and Peripheral Components Figure 4. 44 CPE/EE 421/521 Microcomputers 78

Control Section n n We will divide the memory space $00 0000 - $01 Control Section n n We will divide the memory space $00 0000 - $01 FFFF into eight blocks of 16 KB (IC 1 a, b, IC 2 a, IC 3) 16 KBytes of ROM are at $00 0000 to $00 3 FFF Where is the RAM situated? Peripherals? Note: there is no delay applied to DTACK*. What will happen if we access nondecoded memory? CPE/EE 421/521 Microcomputers 79

Control Section Figure 4. 45 CPE/EE 421/521 Microcomputers 80 Control Section Figure 4. 45 CPE/EE 421/521 Microcomputers 80

Different approaches to memory arrangement n Largest memory window (16 KB) [MEMORY GAPS] A Different approaches to memory arrangement n Largest memory window (16 KB) [MEMORY GAPS] A 23 A 17 A 16 A 15 A 14 A 13 SELECT DECODER A 1 DECODER CPE/EE 421/521 Microcomputers 81

Different approaches to memory arrangement, cont’d n Smallest memory window (4 KB) [NO MEMORY Different approaches to memory arrangement, cont’d n Smallest memory window (4 KB) [NO MEMORY GAPS] A 23 A 15 A 14 A 13 A 12 A 11 SELECT DECODER A 1 DECODER CPE/EE 421/521 Microcomputers 82

Outline n n n 68000 interface Timing diagram Minimal configuration using the 68000 Extensions Outline n n n 68000 interface Timing diagram Minimal configuration using the 68000 Extensions Exception Processing CPE/EE 421/521 Microcomputers 83

How can we make it better? n n n ROM is EPROM-based, and thus How can we make it better? n n n ROM is EPROM-based, and thus slower With EPROMs from the same generation, we’ll need wait states, maybe even with RAM components Watchdog for non-decoded memory addresses CPE/EE 421/521 Microcomputers 84

How can we make it better? Figure 4. 46 CPE/EE 421/521 Microcomputers 85 How can we make it better? Figure 4. 46 CPE/EE 421/521 Microcomputers 85

How can we make it better? Cont’d n CONTROL OF INTERRUPTS n n Use How can we make it better? Cont’d n CONTROL OF INTERRUPTS n n Use 74 LS 148 priority encoder to provide 7 levels of interrupt EXTERNAL BUS INTERFACE n n CPU can supply only the limited current to drive the bus SOLUTION: Bus drivers (buffers) CPE/EE 421/521 Microcomputers 86

DTACK* Generation n DTACK* generator based on a shift register Figure 4. 72 CPE/EE DTACK* Generation n DTACK* generator based on a shift register Figure 4. 72 CPE/EE 421/521 Microcomputers 87

DTACK* Generation Shift register and its timing diagram CPE/EE 421/521 Microcomputers 88 DTACK* Generation Shift register and its timing diagram CPE/EE 421/521 Microcomputers 88

DTACK* Generation Shift register and its timing diagram CPE/EE 421/521 Microcomputers 89 DTACK* Generation Shift register and its timing diagram CPE/EE 421/521 Microcomputers 89

DTACK* Generation n DTACK* generator based on a counter Figure 4. 74 CPE/EE 421/521 DTACK* Generation n DTACK* generator based on a counter Figure 4. 74 CPE/EE 421/521 Microcomputers 90

Outline n n n 68000 interface Timing diagram Minimal configuration using the 68000 Extensions Outline n n n 68000 interface Timing diagram Minimal configuration using the 68000 Extensions Exception Processing CPE/EE 421/521 Microcomputers 91

Interrupt Processing Mechanism n n Interrupt is an asynchronous event When an interrupt occur, Interrupt Processing Mechanism n n Interrupt is an asynchronous event When an interrupt occur, the computer can: n n Service it Ignore it (for the time being) CPE/EE 421/521 Microcomputers 92

Interrupt Control Interface low p r i o r i t y high Figure Interrupt Control Interface low p r i o r i t y high Figure 4. 9 CPE/EE 421/521 Microcomputers 93

Interrupt processing mechanism, cont’d n 1. 2. 3. 4. Sequence of actions when an Interrupt processing mechanism, cont’d n 1. 2. 3. 4. Sequence of actions when an interrupt is being serviced: The computer completes its current machine-level instruction The contents of PC is saved (on stack) The state of the processor (status word) is saved on the stack Jump to the location of the interrupt handling routine CPE/EE 421/521 Microcomputers 94

Interrupt processing mechanism, cont’d n n The interrupt is transparent to the interrupted program Interrupt processing mechanism, cont’d n n The interrupt is transparent to the interrupted program Interrupt request: n n n Can be deferred or denied When it is deferred, it is said to be masked Special one: nonmaskable interrupt request (NMI) The 68000 NMI: IRQ 7 (MSP 430: RST*/NMI pin) Prioritized interrupts Vectored interrupts n Requesting peripheral identifies itself, CPU doesn’t have to poll the status of each device to discover the interrupter CPE/EE 421/521 Microcomputers 95

The 68000 Interrupt Interface CPE/EE 421/521 Microcomputers 96 The 68000 Interrupt Interface CPE/EE 421/521 Microcomputers 96

The 68000 Interrupt Interface CPE/EE 421/521 Microcomputers 97 The 68000 Interrupt Interface CPE/EE 421/521 Microcomputers 97

The 68000 Interrupt Interface n n Reset, bus error, address error, and trace exceptions The 68000 Interrupt Interface n n Reset, bus error, address error, and trace exceptions take precedence over an interrupt A level 7 interrupt CAN interrupt level 7 interrupt CPE/EE 421/521 Microcomputers 98

Processing the Interrupt CPE/EE 421/521 Microcomputers 99 Processing the Interrupt CPE/EE 421/521 Microcomputers 99

Interrupt Timing Diagram CPE/EE 421/521 Microcomputers 100 Interrupt Timing Diagram CPE/EE 421/521 Microcomputers 100

Vectored Interrupts CPE/EE 421/521 Microcomputers 101 Vectored Interrupts CPE/EE 421/521 Microcomputers 101

Exception Vectors n A vector is associated with each type of exception n n Exception Vectors n A vector is associated with each type of exception n n Vector is the 32 -bit absolute address of the appropriate exception handling routine 256 exception vectors, 32 bits (4 bytes) each, extending from address $00 0000 to $00 03 FF Vectors 0 -63 : EXCEPTIONS Vectors 64 -255 : INTERRUPT HANDLING ROUTINES Difference between the reset vector and all other exceptions: n n It requires 2 longwords Located in SP space (FC = 110); others are in SD space (FC = 101) CPE/EE 421/521 Microcomputers 102

Privileged States and the 68000 User programs operate only CPE/EE 421/521 Microcomputers 103 Privileged States and the 68000 User programs operate only CPE/EE 421/521 Microcomputers 103

Privileged States and the 68000, cont’d An exception always forces the 68000 into the Privileged States and the 68000, cont’d An exception always forces the 68000 into the supervisor state CPE/EE 421/521 Microcomputers 104

The 68000 Exceptions CPE/EE 421/521 Microcomputers 105 The 68000 Exceptions CPE/EE 421/521 Microcomputers 105

Interrupts and Real-time Processing n Multitasking (multiprogramming) n n concurrent execution multiple tasks (processes) Interrupts and Real-time Processing n Multitasking (multiprogramming) n n concurrent execution multiple tasks (processes) resource sharing (multiple users using the same printer) Multiprocessing n n parallel execution multiple PROCESSORS! CPE/EE 421/521 Microcomputers 106

Multitasking n n Operating system (to schedule activities) Interrupt mechanism (to switch between tasks) Multitasking n n Operating system (to schedule activities) Interrupt mechanism (to switch between tasks) CPE/EE 421/521 Microcomputers 107

Real-Time Operating System n Real time - meaningful time n fast enough to influence Real-Time Operating System n Real time - meaningful time n fast enough to influence the system at that moment n n Real-time system n n n space shuttle / chemical plant Optimizes the response time to events Tries to use resources efficiently Multitasking system n n Optimizes resource utilization Tries to provide a reasonable response time CPE/EE 421/521 Microcomputers 108

Real-Time Kernel n n Scheduler is the kernel, nucleus, of a real-time OS Functions Real-Time Kernel n n Scheduler is the kernel, nucleus, of a real-time OS Functions n n a first-level interrupt handler scheduler - the sequence in which tasks are executed READY interprocess communication BLOCKED Task States n n n Ready Running Blocked (dormant) RUNNING CPE/EE 421/521 Microcomputers 109

Tasks n n Volatile portion (PC, status, registers) Task control block (TCB) Figure 6. Tasks n n Volatile portion (PC, status, registers) Task control block (TCB) Figure 6. 25 Task ID n Task block pointer n n n PC SP status register other registers Task status n run / ready / blckd Task priority n Task time allocation n n how many slots CPE/EE 421/521 Microcomputers 110

Exception Handling and Tasks n Preemptive real-time OS: n n n RTC generates periodic Exception Handling and Tasks n Preemptive real-time OS: n n n RTC generates periodic interrupts used by the kernel to locate and run the next task How to deal with other interrupts? n n Service them independently, subject to priority Integrate them into the real-time task structure Vectored interrupt Exception Real-time clock interrupt Turn on ready to run flag of appropriate task Call RT task scheduler and switch tasks RTE CPE/EE 421/521 Microcomputers 111