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Course Introduction Purpose § This training course highlights M 16 C 16 -bit and Course Introduction Purpose § This training course highlights M 16 C 16 -bit and 32 -bit devices recommended for new designs. Objectives § Learn about the M 16 C roadmap and key devices in the product line § Understand the advantages of the R 32 C MCUs Content § 23 pages § 1 question Learning Time § 20 minutes 1 © 2008, Renesas Technology America, Inc. , All Rights Reserved

Renesas MCU & MPU Portfolio RISC 32 -Bit SH-4 A (600 MHz) § Superscalar Renesas MCU & MPU Portfolio RISC 32 -Bit SH-4 A (600 MHz) § Superscalar & MMU § Video and audio processing SH-2, SH-2 A (200 MHz) 32 -Bit RX/600 § High Performance CISC with FPU (200 MHz) R 32 C H 8 SX (80 MHz) RX/200 (80 MHz) CISC (50 MHz) 16 -Bit § Application specific integration M 16 C H 8 S (32 MHz) (35 MHz) § Scalable solutions for general purpose 8 -Bit R-Secure (20 MHz) H 8 (20 MHz) R 8 C (20 MHz) § Lowest cost MCUs 2 © 2008, Renesas Technology America, Inc. , All Rights Reserved

M 16 C Platform Compatibility 3 © 2008, Renesas Technology America, Inc. , All M 16 C Platform Compatibility 3 © 2008, Renesas Technology America, Inc. , All Rights Reserved

M 16 C Product Updates 4 © 2008, Renesas Technology America, Inc. , All M 16 C Product Updates 4 © 2008, Renesas Technology America, Inc. , All Rights Reserved

M 16 C Product Update 5 © 2008, Renesas Technology America, Inc. , All M 16 C Product Update 5 © 2008, Renesas Technology America, Inc. , All Rights Reserved

M 16 C Pin compatibility M 16 C/65 M 16 C/64 A Pin Co M 16 C Pin compatibility M 16 C/65 M 16 C/64 A Pin Co mpatib ility M 16 C/62 P 3 4 5 6 7 8 9 96 2 97 6 © 2008, Renesas Technology America, Inc. , All Rights Reserved 1 98 P 94/DA 1/TB 4 IN P 93/DA 0/TB 3 IN P 92/TB 2 IN/SOUT 3 P 91/TB 1 IN/SIN 3 P 90/TB 0 IN/CLK 3 BYTE CNVSS P 87/XCIN P 86/XCOUT 99 100 PWM 1 + PWM 2 + PMC 0 + PMC 1 +

M 16 C/6 x Compatibility M 16 C/63 Operating frequency: 20 MHz 1. 8 M 16 C/6 x Compatibility M 16 C/63 Operating frequency: 20 MHz 1. 8 V Operation RTC : Full Calendar Key on wakeup : +4 M 16 C/65 Operating frequency: 32 MHz(PLL) Upper Compatible M 16 C/64 A On-chip Osc. Operating frequency: 25 MHz(PLL) M 16 C/62 P Operating frequency: 24 MHz(PLL) M 16 C/30 P Operating frequency : 16 MHz DMAC : 2 ch 10 bit. A/D : 18 ch UART/SIO : 3 ch Timer : 6 ch EXT-INT : 6 ch WDT CRC 10 bit. A/D : + 8 ch 8 bit. D/A : 2 ch SIO : + 2 ch Timer : + 5 ch Three phase inverter control LVD : 2 Level On-chip Osc. : 1 ch Data Flash : 4 KB DMAC : + 2 ch RTC : 1 week UART/SIO : + 3 ch Multi-Master I 2 C Bus : 1 ch EXT-INT : + 2 ch Data Flash : +4 KB +CEC H/W Remote control circuit POR On-chip Osc. : +125 k. Hz PWM : 8 bitx 2 ch LVD : + 1 Level User Boot : 16 KB On-chip Debugger *M 16 C/30 B @ 32 MHz Pin Compatibility 7 © 2008, Renesas Technology America, Inc. , All Rights Reserved : +40 MHz

M 16 C Applications White Goods Utility Metering Washer, Dryer, Dishwasher, Oven, Hob, Refrigerator, M 16 C Applications White Goods Utility Metering Washer, Dryer, Dishwasher, Oven, Hob, Refrigerator, Freezer Gas, Water, Electricity, Heat Power Meter AMR (Automated Meter Reading) Automotive Health Monitoring Engine Control, Airbags, In-chassis Networking CIS, Car Audio Fitness/ Glucose Measurement PC and Server Security Pain relief/Muscle Stimulation Keyboard and Power Management Authentication and Security Fire + Burglar Detection Systems Sensors, CCTV HVAC (Heating, Ventilation, AC) e. POS/Barcode Heating, Ventilation, Air Conditioning, Boiler Control Card Readers, Cash Registers, Bar Code Readers, Money Handling, Vending Building Automation Industrial Vehicle, Machine Control Equipments, Robotics, Temperature/Lighting Control, House-Keeping Network, Elevators 8 © 2008, Renesas Technology America, Inc. , All Rights Reserved

M 16 C/5 x, /6 x Series Package Options 64 pins LQFP 80 pins M 16 C/5 x, /6 x Series Package Options 64 pins LQFP 80 pins LQFP ☆: In planning 100 pins LQFP 100 pins QFP 14 x 14 mm 0. 5 mm pitch 14 x 20 mm 0. 65 mm pitch /6 C /65 /64 A /63 128 pins LQFP PKG 10 x 10 mm 0. 5 mm pitch 14 x 14 mm 0. 65 mm pitch 12 x 12 mm 0. 5 mm pitch /65 /63 /56 /5 L /65 /56 /5 L 14 x 20 mm 0. 5 mm pitch /5 L 64 80 100 9 © 2008, Renesas Technology America, Inc. , All Rights Reserved 128 [pins]

M 16 C Next Generation Memory Map 272 -KB (e. g. ) 256 -KB M 16 C Next Generation Memory Map 272 -KB (e. g. ) 256 -KB version M 16 C/65 M 16 C/62 P SFR Internal RAM 64 Kbytes Reserved area Internal ROM 64 Kbytes Data Flash Doubles SFR Internal ROM (4 KBX 2 Data area) (4 KB Data area) Reserved area Internal ROM 64 Kbytes 256 KB 32 Kbytes External area Reserved area 8 Kbytes Internal ROM (Program area) (16 KB Program 2 area) Reserved area 256 KB External area Reserved area 64 Kbytes 8 Kbytes 4 Kbytes 64 Kbytes External area Bo o Sp Mo t Lo ec ve ad ia s t er l. R o eg io n External area 64 Kbytes Internal ROM (Program 1 area) Available Program Area is Same 4 Kbytes 10 © 2008, Renesas Technology America, Inc. , All Rights Reserved

M 16 C/60 CPU Core (16 -bit) Clock generation circuit • 32 MHz, 2. M 16 C/60 CPU Core (16 -bit) Clock generation circuit • 32 MHz, 2. 7 -5. 5 V • Main clock with Xin/Xout • Sub clock with Xcin/Xcout • Fast OCO with 40 MHz • Slow OCO with 125 k. Hz • PLL frequency synthesizer • POR and LVD Peripherals 64 pin 80 pin • Timers • Timer A 16 bit 5 ch • Timer B 16 bit 3 ch • Timer S 16 bit (Capture/Compare) 1 ch • Timer RTC 1 ch • Three phase motor control 1 ch • Serial I/O • USART, I 2 C, IEBus 4 ch 5 ch • Multi Master I 2 C 1 ch • DMA 4 ch • Watchdog Timer (also with OCO) 1 ch • A/D Converter (two circuit with 10 Bit) 16 ch 27 ch max. conv. speed: 1. 6 us/25 MHz • I/O ports • LED port 20 m. A/port (total max. 80 m. A) • CAN RCANII module on M 16 C/5 L 57 pins 73 pins M 16 C/56 & /5 L block diagram Timer A (5 ch, 16 bit) M 16 C CPU Core Timer B (3 ch, 16 bit) 32 [email protected] 2. 7 -5. 5 V Three-phase motor control timer DMA 4 ch Main clock Sub clock On-chip clock PLL 5 ch USART, I 2 C, IEBus Watchdog Timer 15 bit 1 ch Multi Master I 2 C (1 ch, 16 bit) CAN 2. 0 B optional Improved On chip debug Multiplier A/D (10 -bit, 27 ch) Improved LVD/POR CRC Timer S (1 ch, 16 bit) Timer RTC Program ROM II 16 k. B Flash up to 256 k. B Data Flash 2 x 4 k. B block RAM up to 20 k. B 73 I/O pins Memory Package • 64 P 6 Q LQFP (10 mm x 10 mm) @ 0. 5 mm pitch • 80 P 6 Q LQFP (12 mm x 12 mm) @ 0. 5 mm pitch • Flash • RAM • Data Flash • User Boot area 64 k. B-256 k. B 8 k. B-20 k. B 2 x 4 k. B 16 KB 11 © 2008, Renesas Technology America, Inc. , All Rights Reserved

Clock generation circuit • Main clock with Xin/Xout • Sub clock with Xcin/Xcout • Clock generation circuit • Main clock with Xin/Xout • Sub clock with Xcin/Xcout • Slow OCO with 125 k. Hz • PLL frequency synthesizer • POR and LVD M 16 C/60 CPU Core (16 -bit) • 25 MHz, 2. 7 -5. 5 V Mode • Single chip • memory expansion • microprocessor mode Peripherals • Timer A 16 bit • Timer B 16 bit • Timer RTC (1 week timer) • Three phase motor control • Serial I/O • USART, I 2 C, IEBus • SIO • Multi Master I 2 C • DMA • Watchdog Timer 15 bit • A/D Converter 10 bit max. conversion speed: 1. 72 us • D/A Converter 8 bit • I/O ports • CEC and Remote Control Interface • Interrupts (7 priority levels) • Interrupt Vectors • External sources • CRC (CRC-CCITT) M 16 C/64 A block diagram Timer A (5 ch, 16 bit) M 16 C CPU Core 100 pin Timer B (6 ch, 16 bit) 25 [email protected] 2. 7 -5. 5 V 5 ch 6 ch 1 ch Three-phase motor control timer DMA 4 ch Main clock Sub clock On-chip clock PLL 6 ch USART, I 2 C, IEBus 2 ch SIO A/D (10 -bit, 26 ch) Watchdog Timer 15 bit On chip debug D/A (8 bit, 2 ch) 16 bit Multiplier LVD/POR Remote Control CEC CRC 2 ch 89 pins 1 ch Multi Master I 2 C (1 ch, 16 bit) Timer RTC 70 13 1 ch Flash up to 512 k. B Data Flash 2 x 4 k. B block 6 ch 2 ch 1 ch 4 ch 1 ch 26 ch Package • 100 P 6 Q LQFP (14 mm x 14 mm) @ 0. 5 mm pitch • 100 P 6 S QFP (14 mm x 20 mm) @ 0. 65 mm pitch 89 I/O pins Memory • Flash • RAM • Data Flash • User Boot area 12 128 k. B, 256 k. B, 512 k. B, 16 k. B, 31 k. B 2 x 4 k. B 16 KB © 2008, Renesas Technology America, Inc. , All Rights Reserved Program ROM II 16 k. B RAM up to 31 k. B

Clock generation circuit • Main clock with Xin/Xout • Sub clock with Xcin/Xcout • Clock generation circuit • Main clock with Xin/Xout • Sub clock with Xcin/Xcout • Fast OCO with 40 MHz • Slow OCO with 125 k. Hz • PLL frequency synthesizer • POR and LVD Peripherals • Timer A 16 bit • Timer B 16 bit • Timer RTC (1 week timer) • Three phase motor control • Serial I/O • USART, I 2 C, IEBus • SIO • Multi Master I 2 C • DMA • Watchdog Timer 15 bit • A/D Converter 10 bit M 16 C/60 CPU Core (16 -bit) • 32 MHz, 2. 7 -5. 5 V Mode • Single chip • memory expansion • microprocessor mode M 16 C/65 block diagram Timer A (5 ch, 16 bit) M 16 C CPU Core 100 pin Timer B (6 ch, 16 bit) 32 [email protected] 2. 7 -5. 5 V 5 ch 6 ch 1 ch Three-phase motor control timer 4 ch 6 ch USART, I 2 C, IEBus 2 ch SIO A/D (10 -bit, 26 ch) Watchdog Timer 15 bit On chip debug D/A (8 bit, 2 ch) 16 bit Multiplier LVD/POR Remote Control CEC CRC 1 ch Multi Master I 2 C (1 ch, 16 bit) Timer RTC Flash up to 768 k. B 6 ch 2 ch 1 ch 4 ch 1 ch 26 ch max. conversion speed: 1. 72 us • D/A Converter 8 bit 2 ch • I/O ports 89 pins • CEC and Remote Control Interface • Interrupts (7 priority levels) • Interrupt Vectors 70 • External sources 13 • CRC (CRC-CCITT) 1 ch • On-chip debugger Package • 80 P 6 S QFP (14 mm x 14 mm) @ 0. 65 mm pitch • 100 P 6 Q LQFP (14 mm x 14 mm) @ 0. 5 mm pitch • 100 P 6 S QFP (14 mm x 20 mm) @ 0. 65 mm pitch • 128 P 6 Q LQFP (14 mm x 20 mm) @ 0. 5 mm pitch DMA Main clock Sub clock On-chip clock PLL Data Flash 2 x 4 k. B block 13 16 k. B RAM up to 47 k. B 89 I/O pins Memory • Flash • RAM • Data Flash • User Boot area Program ROM II 128 k. B, 256 k. B, 384 k. B, 512 k. B, 640 k. B, 768 k. B 12 k. B, 20 k. B, 31 k. B, 47 k. B 2 x 4 k. B 16 KB © 2008, Renesas Technology America, Inc. , All Rights Reserved

Clock generation circuit • Main clock with Xin/Xout • Sub clock with Xcin/Xcout • Clock generation circuit • Main clock with Xin/Xout • Sub clock with Xcin/Xcout • Fast OCO with 40 MHz • Slow OCO with 125 k. Hz • PLL frequency synthesizer • POR and LVD Peripherals • Timer A 16 bit • Timer B 16 bit • Calendar RTC • Three phase motor control • Serial I/O • USART, I 2 C, IEBus • SIO • Multi Master I 2 C • DMA • Watchdog Timer 15 bit • A/D Converter 10 bit M 16 C/60 CPU Core (16 -bit) • 20 MHz, 2. 7 -5. 5 V • 5 MHz, 1. 8 V-5. 5 V Mode • Single chip • memory expansion • microprocessor mode 100 pin Timer A (5 ch, 16 bit) Timer B (6 ch, 16 bit) Three-phase motor control timer 5 ch 6 ch 1 ch M 16 C CPU Core 20 [email protected] 2. 7 -5. 5 V 10 [email protected] 8 V DMA 4 ch Main clock Sub clock On-chip clock PLL 6 ch USART, I 2 C, IEBus 2 ch SIO A/D (10 -bit, 26 ch) Watchdog Timer 15 bit On chip debug D/A (8 bit, 2 ch) 16 bit Multiplier LVD/POR Remote Control CEC CRC 1 ch Multi Master I 2 C (1 ch, 16 bit) Calendar RTC Flash up to 512 k. B 6 ch 2 ch 1 ch 4 ch 1 ch 26 ch max. conversion speed: 1. 72 us • D/A Converter 8 bit 2 ch • I/O ports 89 pins • CEC and Remote Control Interface • Interrupts (7 priority levels) • Interrupt Vectors 70 • External sources 13 • CRC (CRC-CCITT) 1 ch • On-chip debugger Package • 80 P 6 Q LQFP (10 mm x 10 mm) @ 0. 5 mm pitch • 80 P 6 S QFP (14 mm x 14 mm) @ 0. 65 mm pitch • 100 P 6 Q LQFP (14 mm x 14 mm) @ 0. 5 mm pitch • 100 P 6 S QFP (14 mm x 20 mm) @ 0. 65 mm pitch M 16 C/63 block diagram Data Flash 2 x 4 k. B block Program ROM II 16 k. B RAM up to 31 k. B 89 I/O pins Memory • Flash • RAM • Data Flash • User Boot area 14 © 2008, Renesas Technology America, Inc. , All Rights Reserved 128 k. B, 256 k. B, 384 k. B, 512 k. B, 20 k. B, 31 k. B 2 x 4 k. B 16 KB

R 32 C, the 32 -bit M 16 C Product 15 © 2008, Renesas R 32 C, the 32 -bit M 16 C Product 15 © 2008, Renesas Technology America, Inc. , All Rights Reserved

R 32 C Family overview 16 © 2008, Renesas Technology America, Inc. , All R 32 C Family overview 16 © 2008, Renesas Technology America, Inc. , All Rights Reserved

R 32 C/11 x Series Package Development Plan PKG 64 pins LQFP 80 pins R 32 C/11 x Series Package Development Plan PKG 64 pins LQFP 80 pins LQFP 10 x 10 mm 0. 5 mm pitch 12 x 12 mm 0. 5 mm pitch ☆: In planning 100 pins LQFP 5. 5 x 5. 5 mm 0. 5 mm pitch 144 pins LQFP 176 pins LQFP 14 x 14 mm 0. 5 mm pitch 100 pins FLGA 20 x 20 mm 0. 5 mm pitch 24 x 24 mm 0. 5 mm pitch ☆ /118 A /117 A /116 A /118 /117 /116 /111 64 80 100 17 © 2008, Renesas Technology America, Inc. , All Rights Reserved 144 176 [pins]

Clock generation circuit • Main clock with Xin/Xout • Sub clock with Xcin/Xcout • Clock generation circuit • Main clock with Xin/Xout • Sub clock with Xcin/Xcout • OCO (~125 k. Hz) • PLL frequency synthesizer R 32 C/100 CPU Core (32 -bit) • 50 MHz, 3 V to 5 V R 32 C/111 block diagram Mode • Single chip Main clock Timer A R 32 C/100 • memory expansion (100 -pin) Sub clock (5 ch, 16 bit) CPU Core • microprocessor mode (100 -pin) OCO 50 MHz @ PLL 100 pin 80 pin 64 pin Timer B 3 V-5 V (6 ch, 16 bit) 5 ch 5 ch 9 ch USART, I 2 C, Three-phase 6 ch 5 ch IEBus DMA 4 ch 1 ch 1 ch motor control timer 9 ch 7 ch 6 ch Watchdog A/D 4 ch 4 ch CRC unit Timer 15 bit (10 -bit, 26 ch) 1 ch 1 ch 26 ch 20 ch D/A 32 bit Multiplier DMA II 2 ch 1 ch (8 bit, 2 ch) 84 pins 68 pins 52 pins Peripherals • Timer A 16 bit • Timer B 16 bit • Three phase motor control • Serial I/O • USART , I 2 C, IEBus, Ir. DA • DMA II • Watchdog Timer • A/D Converter (10 Bit) • D/A Converter (8 bit) • I/O ports • Interrupts (7 priority levels) • Interrupt Vectors • External sources • CRC (CRC-CCITT) • X-Y converter (16 bit x 16 bit) • Intelligent I/O • Time measurement function • Waveform generating function • Communication function • On-chip debugger 261 11 1 ch 1 ch 3 ch 16 ch 19 ch 1 ch 261 11 1 ch 3 ch 16 ch 19 ch 1 ch On-chip. Debug 32 bit Barrel Shifter LVD X-Y converter FPU 3 ch Intelligent I/O Flash up to 512 k. B Data. Flash 2 x 4 k. B block RAM up to 63 k. B 84 I/O pins Package • 64 P 6 Q LQFP (12 mm x 12 mm) @ 0. 5 mm pitch • 80 P 6 Q LQFP (14 mm x 14 mm) @ 0. 5 mm pitch • 100 F 0 M FLGA (5. 5 mm x 5. 5 mm) @ 0. 5 mm pitch Memory • Flash • RAM • Data Flash 18 © 2008, Renesas Technology America, Inc. , All Rights Reserved 128 k. B-512 k. B 32 k. B-63 k. B 2 x 4 k. B

Clock generation circuit • Main clock with Xin/Xout • Sub clock with Xcin/Xcout • Clock generation circuit • Main clock with Xin/Xout • Sub clock with Xcin/Xcout • OCO (~125 k. Hz) • PLL frequency synthesizer R 32 C/100 CPU Core (32 -bit) • 50 MHz, 3 V to 5 V Mode • Single chip • memory expansion • microprocessor mode Peripherals • Timer A 16 bit 5 ch • Timer B 16 bit 6 ch • Three phase motor control 1 ch • Serial I/O • USART , I 2 C, IEBus, Ir. DA 9 ch • IIC Multi. Master I/F 1 ch • DMA 4 ch • DMA II • Watchdog Timer 1 ch • A/D Converter (10 Bit) 34 ch • D/A Converter (8 bit) 2 ch • I/O ports 122 pins • 5 V tolerant I/O ports • Interrupts (7 priority levels) • Interrupt Vectors 61 • External sources 10 • CRC (CRC-CCITT) 1 ch • X-Y converter (16 bit x 16 bit) 1 ch • Intelligent I/O 3 ch • Time measurement function 16 ch • Waveform generating function 19 ch • Communication function 1 ch • CAN 0 ch (R 32 C/116); 1 ch (R 32 C/117); 2 ch (R 32 C/118) Package • 100 P 6 Q LQFP (14 mm x 14 mm) @ 0. 5 mm pitch • 144 P 6 Q LQFP (20 mm x 20 mm) @ 0. 5 mm pitch R 32 C/116 -118 block diagram Timer A (5 ch, 16 bit) Timer B (6 ch, 16 bit) Three-phase motor control timer A/D (10 -bit, 26 ch) R 32 C/100 CPU Core 50 MHz @ Main clock Sub clock OCO PLL 3 V-5 V DMA 4 ch 9 ch USART, I 2 C, IEBus Watchdog Timer 15 bit CRC unit D/A (8 bit, 2 ch) 32 bit Multiplier DMA II X-Y converter FPU 3 ch Intelligent I/O On-chip. Debug 32 bit Barrel Shifter LVD I 2 C Multi. Master 1 ch CAN 0 ch, 1 ch or 2 ch 5 V tolerant I/O ports Data. Flash 2 x 4 k. B block RAM up to 63 k. B Flash up to 1 MB 122 I/O pins 19 Memory • Flash • RAM • Data Flash © 2008, Renesas Technology America, Inc. , All Rights Reserved 384 k. B-1 MB 40 k. B-63 k. B 2 x 4 k. B

Advantage: R 32 C timer features R 32 C has 11 independent 16 -Bit Advantage: R 32 C timer features R 32 C has 11 independent 16 -Bit timer § Timer A group has 5 timers TA 0. . TA 4 § Timer B group has 6 timers TB 0. . TB 5 Timers can be cascaded to enable longer time periods Timers can be used as free running or reload type Timer clock source can be system clock /1, /2, /4, /6, . . . , /30 or subclock/32 Every timer has its own interrupt vector and start/stop bit. Mode Timer A Group Timer B Group Timer YES Event Counter YES One Shot Out YES NO PWM 8/16 Bit YES NO Pulse Period Measurement NO YES Pulse Width Measurement NO YES 20 © 2008, Renesas Technology America, Inc. , All Rights Reserved

Advantage: R 32 C intelligent I/0 features Major Feature is a “Classic“ IC/OC-Unit Additional Advantage: R 32 C intelligent I/0 features Major Feature is a “Classic“ IC/OC-Unit Additional Feature is “Phase Shift Waveform Output“ usable for Automotive Lighting Control R 32 C I/O is organized in groups § Each group has 1 x 16 -Bit free running base timer § Each group has 8 channels IC/OC with 8 x 16 -Bit Register for time measurement / waveform generation § 1 Channel IC/OC Function share 1 pin § Each Channel can be individually configured as IC or OC 21 © 2008, Renesas Technology America, Inc. , All Rights Reserved

Advantage: R 32 C UART Module Features R 32 C has 9 independent UART Advantage: R 32 C UART Module Features R 32 C has 9 independent UART modules § All of them LIN V 2. 0 capable Every UART has its own interrupt vector set § Receive Interrupt § Transmit Interrupt 8 -Bit baudrate divider 0. . 255 Buffer register for continuous transmit and receive 22 © 2008, Renesas Technology America, Inc. , All Rights Reserved

Advantage: FPU features R 32 C/100 supports built in floating point unit (FPU) with Advantage: FPU features R 32 C/100 supports built in floating point unit (FPU) with single precision R 32 C/100 FPU Supported Instructions CNVIF: Convert integer to float ROUND: Convert float to signed integer ADDF: Add floating Point SUBF: Subtract floating point MULF: Multiply floating point DIVF: Divide floating point CMPF: Compare floating Point R 32 C’s FPU reduces floating math from >50 instructions to 1! 23 © 2008, Renesas Technology America, Inc. , All Rights Reserved

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