Converter Design Review, October 31, 2007 Josh Myers, Richard Mc. Carthy, Paul Schwinberg, Daniel Sigg, G 070701 -00 -D Advanced LIGO
Initial LIGO Limitations q Collocation of analog and digital Ø Signals converge at converter nodes q Limited timing support Ø Clock input only, no synchronization input, Rely on cycle count q Poor noise performance Ø Sophisticated whitening & dewhitening filters, switchable q Inadequate throughput Ø VME bus latency limitations, 4 boards max. q Convoluted data paths Ø Network topology grew over time, Reflective memory limitations q High costs Ø Dependent on a single manufacturer G 070701 -00 -D Advanced LIGO 2
Requirements q Timing Ø Absolute timing precision relative to UTC: 1μs Ø Guaranteed (no counting of cycles forever) Ø Latency between converter and processor: < 5μs q Noise Ø Converter range: ± 10 V SE or ± 20 V DE Ø Converter noise: 100– 300 n. V/√Hz (SE, best effort) Ø No electrical connection between converters and processors (fiber) q Others Ø No restriction on converter location Ø Detection of transmission errors Ø Support for diagnostics G 070701 -00 -D Advanced LIGO 3
State of Technology q SD-Modulators Ø Typically paired with FIR filters, long delays q SAR (Successive Approximation Register) Ø Analog Devices AD 7634: 18 bit, 570 k. Hz, SNR 101 d. B q Advanced Segment Ø TI PCM 1794 A, 24 bit, 200 k. Hz, SNR 132 d. B (A-weighted / f. Nyquist~12 k. Hz) q Sweet spot around ½ MHz sampling rate G 070701 -00 -D Advanced LIGO 4
PCM 1794 16 bit AD 7634 PCI 66 -16 AI 64 Pentek ADC G 070701 -00 -D Advanced LIGO 5
Comparison Device Noise Range Ratio I/O Price 15 m. V/√Hz 10 Vpp 107 d. B/Hz 8/8 8000 300 n. V/√Hz 4 Vpp 133 d. B/Hz 32/0 10000 5 m. V/√Hz 10 Vpp 117 d. B/Hz 8/8 8000 500 n. V/√Hz 20 Vpp 143 d. B/Hz 0/8 8000 PCI 66 -16 AI 64 SSA (16 k. Hz/131 k. Hz) 10 m. V/√Hz 3. 5 m. V/√Hz 40 Vpp 123 d. B/Hz 132 d. B/Hz 32/0 3900 PCI 66 -16 AO 16 ~1 m. V/√Hz 20 Vpp 137 d. B/Hz 0/16 3500 D 060535 (ADC) 320 n. V/√Hz 40 Vpp 153 d. B/Hz 16/0 2000 D 060293 (DAC) ~200 n. V/√Hz 40 Vpp 157 d. B/Hz 0/16 2000 Pentek 6102 ADC ICS-110 B (SD) Pentek 6102 DAC FDI DAC Commercial: In-House: G 070701 -00 -D Advanced LIGO 6
ADC Performance G 070701 -00 -D Advanced LIGO 7
DAC Performance G 070701 -00 -D Advanced LIGO 8
In-House System Sensor Whitening analog Actuator AA G 070701 -00 -D ADC analog Dewhite AI FPGA digital DAC fiber CPU FPGA No Anti-Aliasing Boards No Anti-Image Boards Strongly Reduced Whitening Reduced Dewhitening Advanced LIGO 9
Whitening/Dewhitening q Compress the analog signal to fit the digital SNR AS port whitening Coil driver dewhitening Pentek ADC → D 060535: Win 45 d. B! FDI DAC → D 060293: Win 10 -20 d. B G 070701 -00 -D Advanced LIGO 10
Integrated Timing q Converter Clock Ø VCXO locked to timing receiver Ø FPGA clock & converter clock are the same q Synchronization Ø 1 PPS signal from timing receiver Ø FPGA counters are synchronized by 1 PPS q Data Transfer Ø Full time stamp on both send and receive Ø Sender deterministic Ø Receiver time stamp checked against allowed time interval Timing is guaranteed in hardware! G 070701 -00 -D Advanced LIGO 11
ADC Board (D 060535) q q 16 channels input Analog front-end Ø Fully differential, 40 Vpp Ø 5 th order Cheby, 200 k. Hz, 0. 5 d. B ripple q q 524288 Hz sampling rate Analog Devices AD 7634 Onboard voltage regulators & reference LVDS interface to FPGA G 070701 -00 -D Advanced LIGO 12
Regulators Channel 1 Reference LVDS Input EEPROM Channel 16 G 070701 -00 -D LVDS Translators Advanced LIGO 13
DAC Board (D 060293) q q 16 channels output Analog front-end Ø Fully differential, 40 Vpp Ø 5 th order Cheby, 53 k. Hz, 0. 1 d. B ripple q q 524288 Hz sampling rate (64 k. Hz bandwidth) Texas Instruments PCM 1794 A Onboard voltage regulators & reference LVDS interface from FPGA G 070701 -00 -D Advanced LIGO 14
Channel 16 Reference EEPROM LVDS Translators LVDS Output Regulators G 070701 -00 -D Advanced LIGO Channel 1 15
Low-Drop Low-Noise Voltage Regulators G 070701 -00 -D Advanced LIGO 16
Crate & Backplane q q Eurocrate IEEE 1101. 1/1101. 10 6 U x 280 mm x 6 HP 2 converters per controller Connectors Ø VME type for converters Ø VME 64 X type for controllers Ø All connections are point-to-point (no bus) q q q 1 unit = 2 controllers + 4 converters ± 16. 5 V, ± 6. 5 V & ± 24 V analog supplies 12 V digital supply → 5 V & 3. 3 V digital G 070701 -00 -D Advanced LIGO 17
Controller Board q Xilinx Spartan 3 A DSP: XC 3 SD 1800 A (2 x) Ø Ø q Xilinx Virtex 4 FX: XC 4 VFX 20 Ø Ø q 37000 logic cells, 84 DSP slices, 1. 5 MBit RAM Converter control: clocks and serial interfaces (LVDS) Filter Engines Time-multiplexed serial links to uplink FPGA 2 x gigabit ethernet SFP transceivers & EMACs Timing transceiver & logic AES/EBU interfaces for mixed analog-digital testing Digital IO lines Digital power supplies Ø 12 V input to 5 V, 3. 3 V, 2. 5 V, 1. 8 V, 1. 5 V, 1. 2 V & whatever Ø Multi-phase synchronous G 070701 -00 -D Advanced LIGO 18
Backplane Links G 070701 -00 -D Advanced LIGO 19
Filter Engine (1) q Multiple second-order sections: q Formula for a single SOS: Ø 4 multiplications with coefficients, old input and old output values Ø 4 accumulations Ø c 0 is a shift operation G 070701 -00 -D Advanced LIGO 20
Filter Engine (2) G 070701 -00 -D Advanced LIGO 21
6 th order elliptic low pass 900 Hz cut-off Filter Engine (3) 35 bit resolution / 18 bit input 52 bit resolution / 27 bit input G 070701 -00 -D Advanced LIGO 22
ADC & DAC Performance q Josh Myers G 070604 -B G 070701 -00 -D Advanced LIGO 23
Development Status q ADC board Ø Prototype and testing done Ø Ready for production with small revisions q DAC board Ø Prototype in hand Ø Testing in progress q Controller board Ø Schematics done Ø Filter engine has been simulated and tested Ø Simulations for uplink code are underway q Crate Ø Backplane defined Ø Thermal loading under investigation Ø Power supplies available as prototype G 070701 -00 -D Advanced LIGO 24
Development Plans q Finished testing of DAC board Ø End of 2007, $7000 if another revision is required q Build and test controller board Ø Manufacturing by Dec 2007, testing by March 2008 Ø Simulation models by Jan 2008 Ø $14000 (two revisions) q Crate Ø Build backplane by Jan 2008, $4000 Ø Assemble prototype crate by Feb 2008, $5000 q Integration Ø Testing with computer back-end by mid 2008, $2000 Ø Small production run for testing at LASTI, 40 m, etc. , $56000 q Test stand for verification and automatic testing Ø Requires outside help, $13000 G 070701 -00 -D Advanced LIGO 25
Conclusions q q q Highest performance ADC and DAC boards Fully integrated timing and synchronization Computer doesn’t see oversampling Ø Works at 16384 Hz and 2048 Hz Ø Compute load at these frequencies shouldn’t be a problem q Design owned by us Ø No dependency on single board manufacturer Ø Person power for in-house development & testing required q q Clear path for future extensions and upgrades Good reasons for adopting this system as the new baseline G 070701 -00 -D Advanced LIGO 26
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