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Constraint-Based Embedded Program Composition NEW IDEAS System SW/HW Description AO Constraint Specs Waveform Descr. Constraint-Based Embedded Program Composition NEW IDEAS System SW/HW Description AO Constraint Specs Waveform Descr. #1 System Design Space/ Embedded Object Specification Constraint Weaver System Composition Waveform Descr. #N System Composition Customized/Optimized Embedded System SW-Based Radio • AO Merging a Model-Based & Language Approaches • Model-Based System Design Space Spec • Textual Constraints/Requirements Spec. • System-Level Constraint Expression Language • AO-Based Strategy Language for Constraint Distribution and Application • Weaver Infrastructure for Automated Constraint Application • Meta-Weaver for Specification of Weavers • Automated Application of RT Constraints IMPACT SCHEDULE • Rapid Construction of Efficient Embedded Systems. • Multiple System Variants for Little Cost. . 3/01 Spec. & Strategy Lang. V 1 • Rapid, Low Cost System Evolution. . 6/01 Constraint Weaver & ATR Demo • Traceabilty from Requirements to Implementation . 3/02 Spec. & Strategy Lang. V 2 • Ability to Customize Tools for Specific Domains . 9/02 Resource Constr. Weaver/Demo • New Design Methodology: AO + Model-Based . 3/03 Complete Spec/Strat Lang. 11/03 Meta-Weaver Descr. . 9/04 SW Radio Demo

Institute for Software Integrated Systems Vanderbilt University Constraint-Based Embedded Program Composition Institute for Software Institute for Software Integrated Systems Vanderbilt University Constraint-Based Embedded Program Composition Institute for Software Integrated Systems Vanderbilt University PI: Ted Bapty Jeff Gray, Sandeep Neema

Project Goals • Investigate the Interactions between MBS+AO • Extend Existing Model-Based Embedded System Project Goals • Investigate the Interactions between MBS+AO • Extend Existing Model-Based Embedded System Design System – Language-based Constraints, – Strategy Language for Constraint Distribution • Customize the tools for Communications • Demonstrate on Software-Based Radio Application

Adaptive Computing Systems Model-Integrated Design Environment Multi-Aspect Modeling Environment Graphical Model Builder System Generation Adaptive Computing Systems Model-Integrated Design Environment Multi-Aspect Modeling Environment Graphical Model Builder System Generation MODELS Behavioral Models Algorithm Models Resource Models Model Analysis Tools SW HW ATR Simulation Environment Reconfigurable Runtime Environment

Model-Integrated Design Environment (MIDE) • Design Capture for HW/SW Codesign: Multiple Aspects – – Model-Integrated Design Environment (MIDE) • Design Capture for HW/SW Codesign: Multiple Aspects – – – Software/Algorithm Data Flow with Multiple Design Alternatives Hardware Resources: Heterogeneous (DSP, RISC, FPGA) Dynamic System Behavior: Multi-modal systems Constraint Specification Language: Link SW/HW/Behavior Result: Comprehensive, Flexible HW/SW System Model • Analysis of Models (Design) – Design-Space Exploration: • Optimize design, select best configurations from alternative designs • Highly scalable using OBDD – Numerical/Algorithmic Simulation with Matlab – Multiple-Resolution Performance Simulation with Discrete Event Simulator

Model-Integrated Design Environment (MIDE) • HW/SW System Synthesis – – – Generate Real-Time Schedules Model-Integrated Design Environment (MIDE) • HW/SW System Synthesis – – – Generate Real-Time Schedules Generate VHDL for FPGA or ASIC Generate Interconnection Topology/Communication Maps Generate Reconfiguration Manager Configuration Result: Functional HW/SW System w/ Dynamic Reconfiguration Capabilities. Compatible with Industry-standard VHDL Compilers • Runtime Support – – – Microkernel for Heterogeneous Distributed DSP’s Virtual Hardware Microkernel for FPGA/ASIC Dynamic System Reconfiguration Controller Real-Time, reconfiguration support. Result: Portable, heterogeneous uniform execution environment

Multiple-View Graphical Modeling/ Flexible Design Space Behavioral Structural Resource Multiple-View Graphical Modeling/ Flexible Design Space Behavioral Structural Resource

Modeling Paradigm Structural/Algorithmic Description Model/Object Hierarchy Example Model Primitive Compound Primitive Template Compound Software Modeling Paradigm Structural/Algorithmic Description Model/Object Hierarchy Example Model Primitive Compound Primitive Template Compound Software Compound Primitive Hardware Primitive Compound Primitive

Defining A Design Space Templates for Algorithm Alternatives Long Range Track Algorithm Alternatives Spatial Defining A Design Space Templates for Algorithm Alternatives Long Range Track Algorithm Alternatives Spatial Domain Sensor Spectral Domain Preprocess Filter Preprocess Image DB XCorr Img Spec DB Error Comp 2 D FFT Mult Error Comp Guidance Loss of Track

Modeling Paradigm Resource Models Network Object Hierarchy Processor Core Example Model Ports FPGA Core Modeling Paradigm Resource Models Network Object Hierarchy Processor Core Example Model Ports FPGA Core ASIC Ports Network Processor ASIC Processor FPGA

Modeling Paradigm Behavioral Description: Hierarchical State Machine Transition Rules Mode A Mode B Transition Modeling Paradigm Behavioral Description: Hierarchical State Machine Transition Rules Mode A Mode B Transition Rules Mode C Attributes Algorithms Performance Specs Constraints (Power/Size/User Defined)

Constraint Modeling S 1 S 2 /e 1[S 21]/ hierarchical parallel FSM Behavior and Constraint Modeling S 1 S 2 /e 1[S 21]/ hierarchical parallel FSM Behavior and Compatibility Constraints /. . / (mode=S 2 implies (Proc. Powr<10)) Power Constraints (mode=(S 1 or S 2))implies(P 1=P 1 i)) P 1 hierarchical interconnect alternatives S 3 Behavior Model /. . / Resource Constraints P 2 Pr 1 (mode!=S 3)implies (Pr 2. assignees =(P 1 i or P 2 j))and(Pr 2=Pr 2 j) Pr 2 P 3 C 1 (D 1. time - D 2. time) < 2 Processing Structure Models Pr 3 Timing Constraints Resource Models

Design Space Exploration Resource Model Binary Encoding BDD Representation Behavior Mod. (Hier. Par. FSM) Design Space Exploration Resource Model Binary Encoding BDD Representation Behavior Mod. (Hier. Par. FSM) Binary Encoding BDD Representation Structural Mod. (Hier. Altern. ) Binary Encoding BDD Representation Constraints (OCL) Binary Encoding BDD Representation Full Symbolic Design Space Pruned Design Space OBDD Analysis

System Synthesis HOST P 1 PC ASIC C 40 DSP BIDIR IFC STREAMS IFC System Synthesis HOST P 1 PC ASIC C 40 DSP BIDIR IFC STREAMS IFC - BIDIR P 1 P 2 XC 4010 FPGA P 3 Kernel Multiple Data Streams P 1 ASIC IFC P 1 IN IFC OUT IFC IN IFC STREAMS IFC OUT P 2 IN IFC STREAMS IFC IN OUT IFC C 40 DSP Real-Time Schedules, Communication Maps P 2 OUT IFC Kernel COMM Interfaces I/O Interfaces P 1 DATA I/O P 2 P 3 I/O Altera FPGA Interfaces VHDL for FPGA Configs

Difficulties in Managing Graphically Specified Constraints Multiple Levels of Hierarchy 4 3 1 c Difficulties in Managing Graphically Specified Constraints Multiple Levels of Hierarchy 4 3 1 c A Replicated Structures B 2 d F e 3’ 1’ Context Sensitive Change Maintenance? ? ? c B 2’ d B e 1’’ c 2’’ d e 4

Constraints Are Critical!! • Define functional properties of system • Ensure proper component interaction Constraints Are Critical!! • Define functional properties of system • Ensure proper component interaction • Designer’s leverage to guide synthesis • Bad Constraint Management = Inflexible, unwieldy development.

Develop Constraint Language Develop Constraint Language

Aspect-Oriented Constraint Language • Develop Language for Specifying Constraints – Operational • Mode-dependent behavior Aspect-Oriented Constraint Language • Develop Language for Specifying Constraints – Operational • Mode-dependent behavior – Performance • Timing • Cost: Power/Parts $/Volume/Weight – Composibility: (Part A ~ Part B, Part C !~ Part D) – Resource: Process X requires Part D – Relationships to Modeling Aspects

Constraint Application Strategy Language • Specify how to apply constraints across object hierarchy. • Constraint Application Strategy Language • Specify how to apply constraints across object hierarchy. • Determines how constraints are divided/responsibility shared among components. • Flexible to permit different goals – Latency optimization – Throughput optimization – ….

Demonstration Plans Waveform #1 Strategy SW “RF” Components Waveform #2 Weaver Unconstrained SW Radio Demonstration Plans Waveform #1 Strategy SW “RF” Components Waveform #2 Weaver Unconstrained SW Radio Real-Time Design Synthesis Runtime Infrastructure