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Computer organization and Architecture Dr. S. K. Malik Department of CSE SRM University, Haryana Computer organization and Architecture Dr. S. K. Malik Department of CSE SRM University, Haryana

Architecture & Organization l Architecture is those attributes visible to the programmer l l Architecture & Organization l Architecture is those attributes visible to the programmer l l l Instruction set, number of bits used for data representation, I/O mechanisms, addressing techniques. e. g. Is there a multiply instruction? Organization is how features are implemented l l Control signals, interfaces, memory technology. e. g. Is there a hardware multiply unit or is it done by repeated addition?

Computer organization Encompasses all physical aspects of computer systems. E. g. , circuit design, Computer organization Encompasses all physical aspects of computer systems. E. g. , circuit design, control signals, memory types. How does a computer work? Computer architecture Logical aspects of system implementation as seen by the programmer. E. g. , instruction sets, instruction formats, data types, addressing modes. How do I design a computer?

The components from which computers are built, i. e. , computer organization. In contrast, The components from which computers are built, i. e. , computer organization. In contrast, computer architecture is the science of integrating those components to achieve a level of functionality and performance. It is as if computer organization examines the lumber, bricks, nails, and other building material While computer architecture looks at the design of the house.

What is What is "Computer Architecture” A system concept integrating software, hardware, and firmware to specify the design of computing systems Application Operating System Compiler Instr. Set Proc. I/O system Digital Design Circuit Design ° Under a set of rapidly changing Forces Instruction Set Architecture

Why study computer organization and architecture? v. Design better programs, including system software such Why study computer organization and architecture? v. Design better programs, including system software such as compilers, operating systems, and device drivers. v. Optimize program behavior. v. Evaluate (benchmark) computer system performance. v. Understand time, space, and price tradeoffs.

Structure & Function • Structure is the way in which components relate to each Structure & Function • Structure is the way in which components relate to each other • Function is the operation of individual components as part of the structure

UNIT-I INTRODUCTION • • • Evolution of Computer Systems Computer Types Functional units Basic UNIT-I INTRODUCTION • • • Evolution of Computer Systems Computer Types Functional units Basic operational concepts Bus structures Memory location and addresses Memory operations Addressing modes Design of a computer system Instruction and instruction sequencing, RISC versus CISC.

Brief History of Computer Evolution Two phases: 1. before VLSI 1945 – 1978 • Brief History of Computer Evolution Two phases: 1. before VLSI 1945 – 1978 • • ENIAC IAS IBM PDP-8 2. VLSI • VLSI = Very Large Scale Integration 1978 present day microprocessors !

Evolution of Computers FIRST GENERATION (1945 – 1955) l l l Program and data Evolution of Computers FIRST GENERATION (1945 – 1955) l l l Program and data reside in the same memory (stored program concepts – John von Neumann) ALP was made used to write programs Vacuum tubes were used to implement the functions (ALU & CU design) Magnetic core and magnetic tape storage devices are used Using electronic vacuum tubes, as the switching components

q. Electronic Numerical Integrator And Computer (ENIAC) built in 1946. q. Size: 30’ x q. Electronic Numerical Integrator And Computer (ENIAC) built in 1946. q. Size: 30’ x 50’ room, 18, 000 vacuum tubes q 1500 relays, weighed 30 tons qdesigners 1. John Mauchly 2. J. Presper Eckert Features of First Generation ØUse of vacuum tubes ØBig & Clumsy ØHigh Electricity Consumption ØProgramming ØLarger ØLot in Mechanical Language AC were needed of electricity failure occurred

SECOND GENERATION (1955 – 1965) l l l Transistor were used to design ALU SECOND GENERATION (1955 – 1965) l l l Transistor were used to design ALU & CU HLL is used (FORTRAN) To convert HLL to MLL compiler were used Separate I/O processor were developed to operate in parallel with CPU, thus improving the performance Invention of the transistor which was faster, smaller and required considerably less power to operate

§Smaller & Cheaper. §Less heat dissipation. §Solid State device. §Transistors Made from Silicon (Sand). §Smaller & Cheaper. §Less heat dissipation. §Solid State device. §Transistors Made from Silicon (Sand). §Invented 1947 at Bell Labs. §William Shockley et al.

THIRD GENERATION (1965 -1975) l l l IC technology improved IC technology helped in THIRD GENERATION (1965 -1975) l l l IC technology improved IC technology helped in designing low cost, high speed processor and memory modules Multiprogramming, pipelining concepts were incorporated DOS allowed efficient and coordinate operation of computer system with multiple users Cache and virtual memory concepts were developed More than one circuit on a single silicon chip became available

FOURTH GENERATION (19751985) l l l CPU – Termed as microprocessor INTEL, MOTOROLA, TEXAS, FOURTH GENERATION (19751985) l l l CPU – Termed as microprocessor INTEL, MOTOROLA, TEXAS, NATIONAL semiconductors started developing microprocessor Workstations, microprocessor (PC) & Notebook computers were developed Interconnection of different computer for better communication LAN, MAN, WAN Computational speed increased by 1000 times Specialized processors like Digital Signal Processor were also developed

BEYOND THE FOURTH GENERATION (1985 – TILL DATE) l l E-Commerce, E- banking, home BEYOND THE FOURTH GENERATION (1985 – TILL DATE) l l E-Commerce, E- banking, home office ARM, AMD, INTEL, MOTOROLA High speed processor - GHz speed Because of submicron IC technology lot of added features in small size

Classes of Computers can be classified, or typed, many ways. Some common classifications are Classes of Computers can be classified, or typed, many ways. Some common classifications are summarized below. Classes by size a. Microcomputers (personal computers) i. Desktop ii. Game console b. Minicomputers (midrange computers) c. Mainframe computers d. Supercomputers Classes by function a. Servers : b. Workstations : c. Information appliances (E. g. Play music) d. Embedded computers:

Classes by Technology a. Analog b. Digital c. Hybrid Classes by Technology a. Analog b. Digital c. Hybrid

Comparisons between different types of computers: Type Components Physical Cost Usage Size and Capacity Comparisons between different types of computers: Type Components Physical Cost Usage Size and Capacity Microcompute r All components in a single unit Smallest Cheapest Minicomputer Several functional units Small Cheap Mainframe computer Several separate units Large Expensive Supercomput er Several separate units Largest Most expensive At homes, in schools and offices In universities, medium-sized companies, departments of large companies In large organizations, universities, government In scientific research, weather forecasting, space exploration, military defense

COMPUTER TYPES Computers are classified based on the parameters like l Speed of operation COMPUTER TYPES Computers are classified based on the parameters like l Speed of operation l Cost l Computational power l Type of application

DESK TOP COMPUTER l l Processing &storage units, visual display &audio uits, keyboards Storage DESK TOP COMPUTER l l Processing &storage units, visual display &audio uits, keyboards Storage media-Hard disks, CD-ROMs Eg: Personal computers which is used in homes and offices Advantage: Cost effective, easy to operate, suitable for general purpose educational or business application NOTEBOOK COMPUTER l l Compact form of personal computer (laptop) Advantage is portability

WORK STATIONS • More computational power than PC • Costlier • Used to solve WORK STATIONS • More computational power than PC • Costlier • Used to solve complex problems which arises in engineering application (graphics, CAD/CAM etc) ENTERPRISE SYSTEM (MAINFRAME) • More computational power • Larger storage capacity • Used for business data processing in large organization • Commonly referred as servers or super computers

SERVER SYSTEM • Supports large volumes of data which frequently need to be accessed SERVER SYSTEM • Supports large volumes of data which frequently need to be accessed or to be modified • Supports request response operation SUPER COMPUTERS • Faster than mainframes • Helps in calculating large scale numerical and algorithm calculation in short span of time • Used for aircraft design and testing, military application and weather forecasting

HANDHELD l l Also called a PDA (Personal Digital Assistant). A computer that fits HANDHELD l l Also called a PDA (Personal Digital Assistant). A computer that fits into a pocket, runs on batteries, and is used while holding the unit in your hand. Typically used as an appointment book, address book, calculator, and notepad. Can be synchronized with a personal microcomputer as a backup.

Basic Terminology l Computer l l A device that accepts input, processes data, stores Basic Terminology l Computer l l A device that accepts input, processes data, stores data, and produces output, all according to a series of stored instructions. l l l Includes the electronic and mechanical devices that process the data; refers to the computer as well as peripheral devices. l A computer program that tells the computer how to perform particular tasks. Network l Hardware l Software Two or more computers and other devices that are connected, for the purpose of sharing data and programs. Peripheral devices l Used to expand the computer’s input, output and storage capabilities.

Basic Terminology l Input l l Data l l Manipulation of the data in Basic Terminology l Input l l Data l l Manipulation of the data in many ways. Memory l l Consists of the processing results produced by a computer. Processing l l The results of the computer storing data as bits and bytes; the words, numbers, sounds, and graphics. Output l l Refers to the symbols that represent facts, objects, or ideas. Information l l Whatever is put into a computer system. Area of the computer that temporarily holds data waiting to be processed, stored, or output. Storage l Area of the computer that holds data on a permanent basis when it is not immediately needed for processing.

Basic Terminology • Assembly language program (ALP) – Programs are written using mnemonics • Basic Terminology • Assembly language program (ALP) – Programs are written using mnemonics • Mnemonic – Instruction will be in the form of English like form • Assembler – is a software which converts ALP to MLL (Machine Level Language) • HLL (High Level Language) – Programs are written using English like statements • Compiler - Convert HLL to MLL, does this job by reading source program at once

Basic Terminology • Interpreter – Converts HLL to MLL, does this job statement by Basic Terminology • Interpreter – Converts HLL to MLL, does this job statement by statement • System software – Program routines which aid the user in the execution of programs eg: Assemblers, Compilers • Operating system – Collection of routines responsible for controlling and coordinating all the activities in a computer system

Computing Systems Computers have two kinds of components: l Hardware, consisting of its physical Computing Systems Computers have two kinds of components: l Hardware, consisting of its physical devices (CPU, memory, bus, storage devices, . . . ) l Software, consisting of the programs it has (Operating system, applications, utilities, . . . )

Functional Units Arithmetic and logic Input Memory Output Control I/O Processor Figure 1. 1. Functional Units Arithmetic and logic Input Memory Output Control I/O Processor Figure 1. 1. Basic functional units of a computer.

Information Handled by a Computer l Instructions/machine instructions Ø Ø Govern the transfer of Information Handled by a Computer l Instructions/machine instructions Ø Ø Govern the transfer of information within a computer as well as between the computer and its I/O devices Specify the arithmetic and logic operations to be performed Program l Data Ø Ø Used as operands by the instructions Source program l Encoded in binary code – 0 and 1 Ø

Memory Unit l Store programs and data Two classes of storage Ø Primary storage Memory Unit l Store programs and data Two classes of storage Ø Primary storage v v Fast Programs must be stored in memory while they are being executed Large number of semiconductor storage cells Processed in words Address RAM and memory access time Memory hierarchy – cache, main memory Ø Secondary storage – larger and cheaper l v v v

Arithmetic and Logic Unit (ALU) l l Most computer operations are executed in ALU Arithmetic and Logic Unit (ALU) l l Most computer operations are executed in ALU of the processor. Load the operands into memory – bring them to the processor – perform operation in ALU – store the result back to memory or retain in the processor. Registers Fast control of ALU

Control Unit l l Ø Ø All computer operations are controlled by the control Control Unit l l Ø Ø All computer operations are controlled by the control unit. The timing signals that govern the I/O transfers are also generated by the control unit. Control unit is usually distributed throughout the machine instead of standing alone. Operations of a computer: Accept information in the form of programs and data through an input unit and store it in the memory Fetch the information stored in the memory, under program control, into an ALU, where the information is processed Output the processed information through an output unit Control all activities inside the machine through a control unit

The processor : Data Path and Control ØTwo types of functional units: Øelements that The processor : Data Path and Control ØTwo types of functional units: Øelements that operate on data values (combinational) Ø elements that contain state (state elements)

Five Execution Steps Step name Action for R-type instructions Action for Memoryreference Instructions Action Five Execution Steps Step name Action for R-type instructions Action for Memoryreference Instructions Action for branches Instruction fetch IR = MEM[PC] PC = PC + 4 Instruction decode/ register fetch Action for jumps A = Reg[IR[25 -21]] B = Reg[IR[20 -16]] ALUOut = PC + (sign extend (IR[15 -0])<<2) Execution, address computation, branch/jump completion ALUOut = A op B ALUOut = A+sign extend(IR[15 -0]) Memory access or R-type completion Reg[IR[15 -11]] = ALUOut Load: MDR =Mem[ALUOut] or Store: Mem[ALUOut] = B Memory read completion Load: Reg[IR[20 -16]] = MDR IF(A==B) Then PC=ALUOut PC=PC[3128]||(IR[250]<<2)

Basic Operational Concepts Basic Operational Concepts

Review l l Activity in a computer is governed by instructions. To perform a Review l l Activity in a computer is governed by instructions. To perform a task, an appropriate program consisting of a list of instructions is stored in the memory. Individual instructions are brought from the memory into the processor, which executes the specified operations. Data to be used as operands are also stored in the memory.

A Typical Instruction l l l Add LOCA, R 0 Add the operand at A Typical Instruction l l l Add LOCA, R 0 Add the operand at memory location LOCA to the operand in a register R 0 in the processor. Place the sum into register R 0. The original contents of LOCA are preserved. The original contents of R 0 is overwritten. Instruction is fetched from the memory into the processor – the operand at LOCA is fetched and added to the contents of R 0 – the resulting sum is stored in register R 0.

Separate Memory Access and ALU Operation l l l Load LOCA, R 1 Add Separate Memory Access and ALU Operation l l l Load LOCA, R 1 Add R 1, R 0 Whose contents will be overwritten?

Connection Between the Processor and the Memory Connection Between the Processor and the Memory

Registers l l l Instruction register (IR) Program counter (PC) General-purpose register (R 0 Registers l l l Instruction register (IR) Program counter (PC) General-purpose register (R 0 – Rn-1) Memory address register (MAR) Memory data register (MDR)

Typical Operating Steps l l l l Programs reside in the memory through input Typical Operating Steps l l l l Programs reside in the memory through input devices PC is set to point to the first instruction The contents of PC are transferred to MAR A Read signal is sent to the memory The first instruction is read out and loaded into MDR The contents of MDR are transferred to IR Decode and execute the instruction

Typical Operating Steps (Cont’) l Get operands for ALU Ø Ø General-purpose register Memory Typical Operating Steps (Cont’) l Get operands for ALU Ø Ø General-purpose register Memory (address to MAR – Read – MDR to ALU) Perform operation in ALU l Store the result back l Ø Ø l To general-purpose register To memory (address to MAR, result to MDR – Write) During the execution, PC is incremented to the next instruction

Interrupt l l Normal execution of programs may be preempted if some device requires Interrupt l l Normal execution of programs may be preempted if some device requires urgent servicing. The normal execution of the current program must be interrupted – the device raises an interrupt signal. Interrupt-service routine Current system information backup and restore (PC, general-purpose registers, control information, specific information)

Bus Structures l l l There are many ways to connect different parts inside Bus Structures l l l There are many ways to connect different parts inside a computer together. A group of lines that serves as a connecting path for several devices is called a bus. Address/data/control

Bus Structure l Single-bus Bus Structure l Single-bus

Speed Issue l l Different devices have different transfer/operate speed. If the speed of Speed Issue l l Different devices have different transfer/operate speed. If the speed of bus is bounded by the slowest device connected to it, the efficiency will be very low. How to solve this? A common approach – use buffers.

Memory Locations, Addresses, and Operations Memory Locations, Addresses, and Operations

Memory Location, Addresses, and Operation n bits l l Memory consists of many millions Memory Location, Addresses, and Operation n bits l l Memory consists of many millions of storage cells, each of which can store 1 bit. Data is usually accessed in n-bit groups. n is called word length. first word second word • • • i th word • • • last word Figure 2. 5. Memory words.

Memory Location, Addresses, and Operation 32 -bit word length example 32 bits b 31 Memory Location, Addresses, and Operation 32 -bit word length example 32 bits b 31 b 30 b 1 • • • l b 0 Sign bit: b 31= 0 for positive numbers b 31= 1 for negative numbers (a) A signed integer 8 bits ASCII character (b) Four characters

Memory Location, Addresses, and Operation l l l To retrieve information from memory, either Memory Location, Addresses, and Operation l l l To retrieve information from memory, either for one word or one byte (8 -bit), addresses for each location are needed. A k-bit address memory has 2 k memory locations, namely 0 – 2 k-1, called memory space. 24 -bit memory: 224 = 16, 777, 216 = 16 M (1 M=220) 32 -bit memory: 232 = 4 G (1 G=230) 1 K(kilo)=210 1 T(tera)=240

Memory Location, Addresses, and Operation l l l It is impractical to assign distinct Memory Location, Addresses, and Operation l l l It is impractical to assign distinct addresses to individual bit locations in the memory. The most practical assignment is to have successive addresses refer to successive byte locations in the memory – byteaddressable memory. Byte locations have addresses 0, 1, 2, … If word length is 32 bits, they successive words are located at addresses 0, 4, 8, …

Big-Endian and Little-Endian Assignments Big-Endian: lower byte addresses are used for the most significant Big-Endian and Little-Endian Assignments Big-Endian: lower byte addresses are used for the most significant bytes of the word Little-Endian: opposite ordering. lower byte addresses are used for the less significant bytes of the word Word address Byte address 0 0 1 2 3 0 3 2 1 0 4 4 5 6 7 4 7 6 5 4 • • • k 2 -4 k 2 -3 • • • k 2 - 2 k 2 - 1 (a) Big-endian assignment k 2 - 4 k 2 - 1 k 2 - 2 k 2 -3 k 2 -4 (b) Little-endian assignment Figure 2. 7. Byte and word addressing.

Memory Location, Addresses, and Operation l l Address ordering of bytes Word alignment l Memory Location, Addresses, and Operation l l Address ordering of bytes Word alignment l Words are said to be aligned in memory if they begin at a byte addr. that is a multiple of the num of bytes in a word. l l 16 -bit word: word addresses: 0, 2, 4, …. 32 -bit word: word addresses: 0, 4, 8, …. 64 -bit word: word addresses: 0, 8, 16, …. Access numbers, characters, and character strings

Memory Operation l Load (or Read or Fetch) Ø Ø Copy the content. The Memory Operation l Load (or Read or Fetch) Ø Ø Copy the content. The memory content doesn’t change. Address – Load Registers can be used l Store (or Write) Ø Overwrite the content in memory Address and Data – Store Registers can be used Ø Ø Ø

Instruction and Instruction Sequencing Instruction and Instruction Sequencing

“Must-Perform” Operations l l Data transfers between the memory and the processor registers Arithmetic “Must-Perform” Operations l l Data transfers between the memory and the processor registers Arithmetic and logic operations on data Program sequencing and control I/O transfers

Register Transfer Notation l l l Identify a location by a symbolic name standing Register Transfer Notation l l l Identify a location by a symbolic name standing for its hardware binary address (LOC, R 0, …) Contents of a location are denoted by placing square brackets around the name of the location (R 1←[LOC], R 3 ←[R 1]+[R 2]) Register Transfer Notation (RTN)

Assembly Language Notation l l l Represent machine instructions and programs. Move LOC, R Assembly Language Notation l l l Represent machine instructions and programs. Move LOC, R 1 = R 1←[LOC] Add R 1, R 2, R 3 = R 3 ←[R 1]+[R 2]

CPU Organization l Single Accumulator l l l General Register l l l Result CPU Organization l Single Accumulator l l l General Register l l l Result usually goes to the Accumulator has to be saved to memory quite often Registers hold operands thus reduce memory traffic Register bookkeeping Stack l Operands and result are always in the stack

Instruction Formats l Three-Address Instructions l l ADD R 1, R 2 R 1 Instruction Formats l Three-Address Instructions l l ADD R 1, R 2 R 1 ← R 1 + R 2 ADD M AC ← AC + M[AR] Zero-Address Instructions l l R 1 ← R 2 + R 3 One-Address Instructions l l R 1, R 2, R 3 Two-Address Instructions l l ADD TOS ← TOS + (TOS – 1) RISC Instructions l Lots of registers. Memory is restricted to Load & Store Opcode Operand(s) or Address(es)

Instruction Formats Example: Evaluate (A+B) (C+D) l Three-Address 1. 2. 3. ADD MUL R Instruction Formats Example: Evaluate (A+B) (C+D) l Three-Address 1. 2. 3. ADD MUL R 1, A, B R 2, C, D X, R 1, R 2 ; R 1 ← M[A] + M[B] ; R 2 ← M[C] + M[D] ; M[X] ← R 1 R 2

Instruction Formats Example: Evaluate (A+B) (C+D) l Two-Address 1. 2. 3. 4. 5. 6. Instruction Formats Example: Evaluate (A+B) (C+D) l Two-Address 1. 2. 3. 4. 5. 6. MOV ADD MUL MOV R 1, A R 1, B R 2, C R 2, D R 1, R 2 X, R 1 ; R 1 ← M[A] ; R 1 ← R 1 + M[B] ; R 2 ← M[C] ; R 2 ← R 2 + M[D] ; R 1 ← R 1 R 2 ; M[X] ← R 1

Instruction Formats Example: Evaluate (A+B) (C+D) l One-Address 1. 2. 3. 4. 5. 6. Instruction Formats Example: Evaluate (A+B) (C+D) l One-Address 1. 2. 3. 4. 5. 6. 7. LOAD A ADD B STORET LOAD C ADD D MUL T STOREX ; AC ← M[A] ; AC ← AC + M[B] ; M[T] ← AC ; AC ← M[C] ; AC ← AC + M[D] ; AC ← AC M[T] ; M[X] ← AC

Instruction Formats Example: Evaluate (A+B) (C+D) l Zero-Address 1. 2. 3. 4. 5. 6. Instruction Formats Example: Evaluate (A+B) (C+D) l Zero-Address 1. 2. 3. 4. 5. 6. 7. 8. PUSH A PUSH B ADD PUSH C PUSH D ADD MUL (C+D) (A+B) POP X ; TOS ← A ; TOS ← B ; TOS ← (A + B) ; TOS ← C ; TOS ← D ; TOS ← (C + D) ; TOS ← ; M[X] ← TOS

Instruction Formats Example: Evaluate (A+B) (C+D) l RISC 1. 2. 3. 4. 5. 6. Instruction Formats Example: Evaluate (A+B) (C+D) l RISC 1. 2. 3. 4. 5. 6. 7. 8. LOAD R 1, A LOAD R 2, B LOAD R 3, C LOAD R 4, D ADD R 1, R 2 ADD R 3, R 4 MUL R 1, R 3 STOREX, R 1 ; R 1 ← M[A] ; R 2 ← M[B] ; R 3 ← M[C] ; R 4 ← M[D] ; R 1 ← R 1 + R 2 ; R 3 ← R 3 + R 4 ; R 1 ← R 1 R 3 ; M[X] ← R 1

Using Registers l l Registers are faster Shorter instructions l l l The number Using Registers l l Registers are faster Shorter instructions l l l The number of registers is smaller (e. g. 32 registers need 5 bits) Potential speedup Minimize the frequency with which data is moved back and forth between the memory and processor registers.

Instruction Execution and Straight-Line Sequencing Address Begin execution here Contents i Move A, R Instruction Execution and Straight-Line Sequencing Address Begin execution here Contents i Move A, R 0 i+4 Add i+8 Move R 0, C B, R 0 3 -instruction program segment A B C Data for the program Assumptions: - One memory operand per instruction - 32 -bit word length - Memory is byte addressable - Full memory address can be directly specified in a single-word instruction Two-phase procedure -Instruction fetch -Instruction execute Page 43 Figure 2. 8. A program for C ¬ [A] + [B].

i Branching Move NUM 1, R 0 i+4 Add NUM 2, R 0 i+8 i Branching Move NUM 1, R 0 i+4 Add NUM 2, R 0 i+8 Add NUM 3, R 0 • • • i + 4 n - 4 Add NUMn, R 0 i + 4 n Move R 0, SUM • • • SUM NUM 1 NUM 2 • • • NUMn Figure 2. 9. A straight-line program for adding n numbers.

Addressing Modes Addressing Modes

Generating Memory Addresses l l l How to specify the address of branch target? Generating Memory Addresses l l l How to specify the address of branch target? Can we give the memory operand address directly in a single Add instruction in the loop? Use a register to hold the address of NUM 1; then increment by 4 on each pass through the loop.

Addressing Modes l l l l Implied Immediate Direct Indirect Register Indirect Displacement (Indexed) Addressing Modes l l l l Implied Immediate Direct Indirect Register Indirect Displacement (Indexed) Stack

Addressing Modes l Implied l l l . . . AC is implied in Addressing Modes l Implied l l l . . . AC is implied in “ADD M[AR]” in “One-Address” instr. TOS is implied in “ADD” in “Zero-Address” instr. Immediate l l Opcode Mode The use of a constant in “MOV R 1, 5”, i. e. R 1 ← 5 Register l Indicate which register holds the operand

Immediate Addressing l l l Operand is part of instruction Operand = address field Immediate Addressing l l l Operand is part of instruction Operand = address field e. g. ADD 5 l l l Add 5 to contents of accumulator 5 is operand No memory reference to fetch data Fast Limited range

Addressing Modes l Register Indirect l Indicate the register that holds the number of Addressing Modes l Register Indirect l Indicate the register that holds the number of the register that holds the operand R 1 MOV l Autoincrement / Autodecrement l l R 1, (R 2) Access & update in 1 instr. R 2 = 3 R 3 = 5 Direct Address l Use the given address to access a memory location

Indirect Addressing l l Memory cell pointed to by address field contains the address Indirect Addressing l l Memory cell pointed to by address field contains the address of (pointer to) the operand EA = (A) l l Look in A, find address (A) and look there for operand e. g. ADD (A) l Add contents of cell pointed to by contents of A to accumulator

Indirect Addressing l l l Large address space 2 n where n = word Indirect Addressing l l l Large address space 2 n where n = word length May be nested, multilevel, cascaded l e. g. EA = (((A))) l l l Draw the diagram yourself Multiple memory accesses to find operand Hence slower

Addressing Modes l Indirect Address l Indicate the memory location that holds the address Addressing Modes l Indirect Address l Indicate the memory location that holds the address of the memory location that holds the data AR = 101 100 101 102 103 104 0 1 0 4 1 1 0 A

Addressing Modes l Relative Address l EA = PC + Relative Addr PC = Addressing Modes l Relative Address l EA = PC + Relative Addr PC = 2 0 1 2 + AR = 100 Could be Positive or Negative (2’s Complement) 100 101 102 103 104 1 1 0 A

Addressing Modes l Indexed l EA = Index Register + Relative Addr Useful with Addressing Modes l Indexed l EA = Index Register + Relative Addr Useful with “Autoincrement” or “Autodecrement” XR = 2 + AR = 100 Could be Positive or Negative (2’s Complement) 100 101 102 103 104 1 1 0 A

Addressing Modes l Base Register l EA = Base Register + Relative Addr Could Addressing Modes l Base Register l EA = Base Register + Relative Addr Could be Positive or Negative (2’s Complement) AR = 2 + BR = 100 Usually points to the beginning of an array 100 101 102 103 104 0 0 0 0 1 0 0 5 5 2 A 7 9

Addressing Modes l The different ways in which the location of an operand is Addressing Modes l The different ways in which the location of an operand is specified in an instruction are referred to as addressing modes. Name Assembler syntax Addressingfunction Immediate #Value Op erand = Value Register Ri EA = Ri Absolute (Direct) LOC EA = LOC Indirect (Ri ) (LOC) EA = [Ri ] EA = [LOC] Index X(R i) EA = [Ri ] + X Basewith index (Ri , Rj ) EA = [Ri ] + [Rj ] Basewith index and offset X(R i, Rj ) EA = [Ri ] + [Rj ] + X Relative X(PC) EA = [PC] + X (Ri )+ EA = [Ri ] ; Increment Ri (Ri ) Decrement R i ; EA = [Ri] Autoincrement Autodecrement

Indexing and Arrays l l l Index mode – the effective address of the Indexing and Arrays l l l Index mode – the effective address of the operand is generated by adding a constant value to the contents of a register. Index register X(Ri): EA = X + [Ri] The constant X may be given either as an explicit number or as a symbolic name representing a numerical value. If X is shorter than a word, sign-extension is needed.

Indexing and Arrays l l In general, the Index mode facilitates access to an Indexing and Arrays l l In general, the Index mode facilitates access to an operand whose location is defined relative to a reference point within the data structure in which the operand appears. Several variations: (Ri, Rj): EA = [Ri] + [Rj] X(Ri, Rj): EA = X + [Ri] + [Rj]

Relative Addressing l l l Relative mode – the effective address is determined by Relative Addressing l l l Relative mode – the effective address is determined by the Index mode using the program counter in place of the general-purpose register. X(PC) – note that X is a signed number Branch>0 LOOP This location is computed by specifying it as an offset from the current value of PC. Branch target may be either before or after the branch instruction, the offset is given as a singed num.

Additional Modes l l l Autoincrement mode – the effective address of the operand Additional Modes l l l Autoincrement mode – the effective address of the operand is the contents of a register specified in the instruction. After accessing the operand, the contents of this register are automatically incremented to point to the next item in a list. (Ri)+. The increment is 1 for byte-sized operands, 2 for 16 -bit operands, and 4 for 32 -bit operands. Autodecrement mode: -(Ri) – decrement first LOOP Move Clear Add Decrement Branch>0 Move N, R 1 #NUM 1, R 2 R 0 (R 2)+, R 0 R 1 LOOP R 0, SUM Initialization Figure 2. 16. The Autoincrement addressing mode used in the program of Figure 2. 12.

Types of Instructions l Data Transfer Instructions Name Mnemonic Load LD Store ST Move Types of Instructions l Data Transfer Instructions Name Mnemonic Load LD Store ST Move MOV Exchange XCH Input IN Output OUT Push PUSH Pop POP Data value is not modified

Data Transfer Instructions Mode Assembly Register Transfer Direct address LD ADR AC ← M[ADR] Data Transfer Instructions Mode Assembly Register Transfer Direct address LD ADR AC ← M[ADR] Indirect address LD @ADR AC ← M[M[ADR]] Relative address LD $ADR AC ← M[PC+ADR] Immediate operand LD #NBR AC ← NBR Index addressing LD ADR(X) AC ← M[ADR+XR] Register LD R 1 AC ← R 1 Register indirect LD (R 1) AC ← M[R 1] Autoincrement LD (R 1)+ AC ← M[R 1], R 1 ← R 1+1

Data Manipulation Instructions l Arithmetic Logical & Bit Manipulation Shift Name Mnemonic Increment INC Data Manipulation Instructions l Arithmetic Logical & Bit Manipulation Shift Name Mnemonic Increment INC l Decrement DEC Add ADD l Subtract SUB Multiply MUL Divide DIV Add with carry ADDC Name Mnemonic Subtract with borrow SUBB Clear CLR Negate NEG Complement COM Name Mnemonic AND Logical shift right SHR OR OR Logical shift left SHL Exclusive-OR XOR Arithmetic shift right SHRA Clear carry CLRC Arithmetic shift left SHLA Set carry SETC Rotate right ROR Complement carry COMC Rotate left ROL Enable interrupt EI Rotate right through carry RORC Disable interrupt DI Rotate left through carry ROLC

Program Control Instructions Name Mnemonic Branch BR Jump JMP Skip SKP Call CALL Return Program Control Instructions Name Mnemonic Branch BR Jump JMP Skip SKP Call CALL Return Compare (Subtract) Test (AND) RET Subtract A – B but don’t store the result CMP 10110001 TST 00001000 Mask 0000

Addressing Modes (Summary) Base register LDA #ADRS(R 1) ACC <- M[R 1+ADRS] Addressing Modes (Summary) Base register LDA #ADRS(R 1) ACC <- M[R 1+ADRS]

Instruction Set Architecture l RISC (Reduced Instruction Set Computer) Architectures l l l Memory Instruction Set Architecture l RISC (Reduced Instruction Set Computer) Architectures l l l Memory accesses are restricted to load and store instruction, and data manipulation instructions are register to register. Addressing modes are limited in number. Instruction formats are all of the same length. Instructions perform elementary operations CISC (Complex Instruction Set Computer) Architectures l l Memory access is directly available to most types of instruction. Addressing mode are substantial in number. Instruction formats are of different lengths. Instructions perform both elementary and complex operations.

Instruction Set Architecture l RISC (Reduced Instruction Set Computer) Architectures Large register file l Instruction Set Architecture l RISC (Reduced Instruction Set Computer) Architectures Large register file l Control unit: simple and hardwired l pipelining l l CISC (Complex Instruction Set Computer) Architectures Register file: smaller than in a RISC l Control unit: often micro-programmed l Current trend l l CISC operation a sequence of RISC-like operations

CISC Examples l Examples of CISC processors are the l l l System/360(excluding the CISC Examples l Examples of CISC processors are the l l l System/360(excluding the 'scientific' Model 44), VAX, PDP-11, Motorola 68000 family Intel x 86 architecture based processors.

Pro’s l l l Emphasis on hardware Includes multi-clock complex instructions Memory-to-memory: Pro’s l l l Emphasis on hardware Includes multi-clock complex instructions Memory-to-memory: "LOAD" and "STORE" incorporated in instructions Small code sizes, high cycles per second Transistors used for storing complex instructions

Con’s l l l That is, the incorporation of older instruction sets into new Con’s l l l That is, the incorporation of older instruction sets into new generations of processors tended to force growing complexity. Many specialized CISC instructions were not used frequently enough to justify their existence. Because each CISC command must be translated by the processor into tens or even hundreds of lines of microcode, it tends to run slower than an equivalent series of simpler commands that do not require so much translation.

RISC Examples l l l l Apple i. Pods (custom ARM 7 TDMI So. RISC Examples l l l l Apple i. Pods (custom ARM 7 TDMI So. C) Apple i. Phone (Samsung ARM 1176 JZF) Palm and Pocket. PC PDAs and smartphones (Intel XScale family, Samsung SC 32442 ARM 9) Nintendo Game Boy Advance (ARM 7) Nintendo DS (ARM 7, ARM 9) Sony Network Walkman (Sony in-house ARM based chip) Some Nokia and Sony Ericsson mobile phones

Pro’s l l l Emphasis on software Single-clock, reduced instruction only Register to register: Pro’s l l l Emphasis on software Single-clock, reduced instruction only Register to register: "LOAD" and "STORE" are independent instructions Low cycles per second, large code sizes Spends more transistors on memory registers

Performance l The CISC approach attempts to minimize the number of instructions per program, Performance l The CISC approach attempts to minimize the number of instructions per program, sacrificing the number of cycles per instruction. RISC does the opposite, reducing the cycles per instruction at the cost of the number of instructions per program.

Characteristics of RISC Vs CISC processors No RISC CISC 1 Simple instructions taking one Characteristics of RISC Vs CISC processors No RISC CISC 1 Simple instructions taking one cycle Complex instructions taking multiple cycles 2 Instructions are executed by hardwired control unit Instructions are executed by microprogramed control unit 3 4 5 Few instructions Many instructions Fixed format instructions Variable format instructions 6 7 Multiple register set Single register set Highly pipelined Not pipelined or less pipelined Few addressing mode, and most Many addressing modes instructions have register to register addressing mode

Instruction Cycle • A computer goes through the following instruction cycle repeatedly: do 1. Instruction Cycle • A computer goes through the following instruction cycle repeatedly: do 1. Fetch an instruction from memory 2. Decode the instruction 3. Read the effective address from memory if the instruction has an indirect address 4. Execute the instruction until a HALT instruction is • The fetch & decode encountered phases of the instruction cycle consists of the following microoperations synchronized with the timing signals (clocking principle). Timing signal T 0: T 1: T 2: IR(15) microoperations AR ¬ PC IR ¬ M[AR], PC ¬ PC + 1 D 0, . . . , D 7 ¬ Decode IR(12 -14), AR ¬ IR(0 -11), I ¬

T 0: Since only AR is connected to the address inputs of memory, the T 0: Since only AR is connected to the address inputs of memory, the address of instruction is transferred from PC to AR. 1. Place the content of PC onto the bus by making the bus selection inputs S 2 S 1 S 0 = 010. 2. Transfer the content of the bus to AR by enabling the LD input to AR ( AR ¬ PC). T 1: The instruction read from memory is then placed in the instruction register IR. At the same time, PC is incremented to prepare for the address of the next instruction. 1. Enable the read input of the memory. 2. Place the content of memory onto the bus by making the bus selection inputs S 2 S 1 S 0 = 111. (Note that the address lines are always connected to AR, and we have already placed the next instruction address in AR. ) 3. Transfer the content of the bus to IR by enabling the LD input to IR (IR ¬ M[AR]). 4. Increment PC by enabling the INR input of PC ( PC ¬ PC + 1 ). T 2: The operation code in IR is decoded; the indirect bit is transferred to I; the address part of the instruction is transferred to AR. (See the common bus skeleton diagram. )

Similar circuits are used to realize the microoperations at T 2. • At T Similar circuits are used to realize the microoperations at T 2. • At T 3, microoperations which take place depend on the type of instruction. The four different paths are symbolized as follows, where the control functions must be connected to the proper inputs to activate the desired microoperations. Control function D 7’IT 3: D 7’I’T 3: D 7 IT 3: instruction Microoperation AR ¬ M[AR], indirect memory transfer Nothing, direct memory transfer Execute a register-reference instruction Execute an I/O When D 7’T 3 = 1 (At T 3 & IR(12 -14) ¹ 111), the execution of memory-reference instructions takes place with the next timing variable T 4.

5. 6 Memory Reference Instructions • Opcode (000 - 110) or the decoded output 5. 6 Memory Reference Instructions • Opcode (000 - 110) or the decoded output Di (i = 0, . . . , 6) are used to select one memory-reference operation out of 7.

5 -6. Memory Reference Instruction STA : memory write Fig. 5 -10 Example of 5 -6. Memory Reference Instruction STA : memory write Fig. 5 -10 Example of BSA l BUN : branch unconditionally PC = 10 PC = 21 l BSA : branch and save return address l 0 BSA 135 next instruction 135 21(return address) PC = 136 Subroutine 1 Return Address : save return address ( 135 l Subroutine Call : Fig. 5 -10 ISZ : increment and skip if zero l l l Control Flowchart : Fig. 5 -11 l Flowchart for the 7 memory reference instruction § The longest instruction : ISZ(T 6) § 3 bit Sequence Counter BUN 135 21 )

Branch and Save Address (BSA) Subroutine implementation using BSA. Branch and Save Address (BSA) Subroutine implementation using BSA.