Computer Architecture Slide Sets WS 2011 2012 Prof Dr

Computer Architecture Slide Sets WS 2011/2012 Prof. Dr. Uwe Brinkschulte Prof. Dr. Klaus Waldschmidt Part 3 Fundamentals in Computer Architecture – Part 3 – page 1 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

Basic definitions Computer Architecture defines the behavior and the attributes of a computer as seen by the programmer and user, no internal structural or organization details Computer Organization the internal organization (datapaths, memory structures, input/output structures, e. g. ) of a computer Computer Architecture – Part 3 – page 2 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

Basic definitions Processor Architecture part of Computer Architecture, defines the view of the processor visible to the programmer or compiler developer, interface between hard- and software, no implementation details Microarchitecture defines the concrete implementation of a processor architecture, several implementations of the same processor architecture might exist (e. g. Intel IA 32) Operation Principle defines the way the processor processes instructions and data Computer Architecture – Part 3 – page 3 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

Basic definitions Software Computer Architecture Hardware Memory Input/ Output Processor Architecture Processor Microarchitecture Operation Principle Computer Organization Computer Architecture – Part 3 – page 4 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

Basic definitions Instruction Set defines the set of instructions executable by the given processor architecture Instruction Set Architecture often used as a synonym to processor (ISA) architecture Instruction Format defines the way operands are accessed by instructions, instructions usually are divided into an opcode (tells what to do) and one ore more operands (tells on what to apply the opcode) Computer Architecture – Part 3 – page 5 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

Basic instruction formats 3 -Address-Format Opcode, Dest, Src 1, Src 2 e. g. add C, B, A (C = A + B) 2 -Address-Format Opcode, Dest/Src 1, Src 2 e. g. add B, A 1 -Address-Format (B = A + B) Opcode, Src e. g. add B (Accu = Accu + B) a special accumulator register (Accu) is used 0 -Address-Format Opcode e. g. push A push B add pop C (C = A + B) Stack based architecture Computer Architecture – Part 3 – page 6 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

More basic definitions Central Processing Unit (CPU, Processor) central unit of a computer, controls all computer operations consists of a control unit and a functional unit Instructions (command) operands (data) control unit functional unit (datapath) The operation principle of a processor can be a sequential or a parallel processing of instructions (the program) The processing in one or more functional units is controlled by the control unit. results Computer Architecture – Part 3 – page 7 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

More basic definitions Microprocessor a CPU on a single chip Microprocessor-System a technical system containing at least one microprocessor (may not be a computer, e. g. a phone) Microcomputer a computer build from one or more micropressors, contains also memory, input/output (IO) and a connection system (bus) Microcomputer-System a microcomputer with attached peripherals (e. g. keyboard, screen, mouse, printer, etc. ) Computer Architecture – Part 3 – page 8 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

More basic definitions Microcomputer Microprocessor, CPU control unit functional unit (datapath) connection (bus) memory (program, data) input/output peripherals Microcomputer-System Computer Architecture – Part 3 – page 9 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

More basic definitions Memory consists of a linear set of memory cells mostly have uniform size (e. g. a byte) memory cells are identified by an address Input/Output interface to the peripherals like memory, IO units are identified by an address data . . . memory IO Computer Architecture – Part 3 – page 10 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

More basic definitions Bus connection system between CPU, memory and IO unit Data Bus part of the bus where data (instructions or operands) is transfered (usually bidirectional) Address Bus part of the bus where address information (memory or IO addresses) is transfered (usual unidirectional) Control Bus part of the bus where control and status signals are transferred (partly unidirectional, partly bidirectional) Data Bus Address Bus Control Bus CPU side Computer Architecture – Part 3 – page 11 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt memory/IO side Hier wird Wissen Wirklichkeit

The Von-Neumann-Architecture • The operation principle of a Von-Neumann-architecture defines that instructions are processed sequentially. • Instructions and data are stored in the same main memory • The opcode is to be applied to the operands. • Depending on the opcode, the operands are interpreted as data or memory addresses of data. • In the latter case, the instruction is applied to the content of the addressed memory cell. Computer Architecture – Part 3 – page 12 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

The Von-Neumann-Architecture • An operand may be interpreted as a jump pointer to an instruction. • Since instructions and data reside in the same memory, a memory address may contain a data value or an instruction. • Interpretation of a memory cell’s content depends on the opcode of the instruction only. CPU address data code main memory Computer Architecture – Part 3 – page 13 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

The Von-Neumann-Architecture program and data memory control unit datapath condition codes control signals Shared memory for program and data, sequential access. micro commands addresses of data or commands processor Von-Neumann. Architecture: • simple structure (only one memory) • program and data must access the memory one after another data and instructions Computer Architecture – Part 3 – page 14 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

Operation Principle of Von-Neumann-Architecture Demonstration data address instruction operand main memory instruction operand result address control unit decode result functional unit (datapath) execute control Von-Neumann bottleneck! Computer Architecture – Part 3 – page 15 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

The Von-Neumann-Architecture necessary sequential steps to execute an instruction 1. Send instruction i address 2. Fetch instruction i 3. Decode instruction i 4. Send operand address i 5. Fetch operand i 6. Execute instruction i 7. Send result address & result i 8. Send instruction address i+1 7 step cycle 9. … Computer Architecture – Part 3 – page 16 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

The Harvard-Architecture program memory data memory processor instructions control unit control signals (program counter, instruction register, control register) condition codes micro instructions results function unit (data path) (data register, ALU, shifter, MUX, DEMUX) instruction address operands control signals The processor is augmented by a program memory which stores the program to be executed. Data is stored in a second memory, the data memory. Harvard-Architecture: • complex structure (two memories) • program and data can access their memories at the same time Computer Architecture – Part 3 – page 17 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

Operation Principle of Havard-Architecture Demonstration data address instruction program memory instruction address operand result address result control unit functional unit (datapath) decode operand data memory execute control Computer Architecture – Part 3 – page 18 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

The Havard-Architecture necessary sequential steps to execute an instruction 1. Send instruction i address 2. Fetch instruction i 3. Decode instruction i 4. Send operand address i 5. Fetch operand i | send instruction i+1 address 6. Execute instruction i | fetch instruction i+1 7. Send result address & result i | decode instruction i+1 8. Send operand address i+1 9. Fetch operand i+1 | send instruction i+2 address 10. Execute instruction i+1 | fetch instruction i+2 11. Send result address & result i+1 | decode instruction i+2 12. … Computer Architecture – Part 3 – page 19 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt i overlap 4 step cycle i+1 Hier wird Wissen Wirklichkeit

• The microprocessor receives the instructions in sequential order from the main memory. Therefore, the control unit contains a program counter (PC) to address the instructions • It decodes each instruction and executes an operation on the content of the memory cell addressed by the instruction. • In Von-Neumann-Architecture, the interpretation of the memory cell’s content (data or instruction) depends only on the information in the instruction. Data and instructions are stored in the main memory in the same way and are indistinguishable from memory side therefore. • The memory cells themselves don’t keep track of the type of their content. • The only structuring is the size of the smallest addressable unit given by the bit width (8, 16, 32, or 64). Computer Architecture – Part 3 – page 20 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

The computer executes three phases which may overlap: • In the instruction retrieval phase the content of a memory cell which is addressed by the program counter is fetched. • In the decode phase the content of the retrieved memory cell is interpreted as an instruction. • In the execution phase the contents of one or two memory cells are fetched and processed depending on the command given by the opcode. It is thereby assumed that the memory cells contain data which are conform to the given preconditions. Computer Architecture – Part 3 – page 21 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

Sequential execution of a program control unit program instruction instr. 1 instr. 2 instr. 3 instr. 4 … … Interpretation of the instruction control commands Computer Architecture – Part 3 – page 22 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

Computer: CPU + Memory Model: Bus complexity: b Bits (word length) bus lines = #b + ld(w) + #control Timing: control W CPU Words address data clock memory address valid read/write control data valid data bus memory access Computer Architecture – Part 3 – page 23 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

CPU as FSMD model (Finite State Machine with Datapath) control flow data flow instruction (program) data in data register state register next state output function data path control functional units data path control unit control commands Computer Architecture – Part 3 – page 24 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt data out Hier wird Wissen Wirklichkeit

Data path (bus oriented) e. g. 2 functional units Register 1 Register 2 Register 3 switches (tri state) control lines operand registers FU 1 FU 2 bus lines functional units Computer Architecture – Part 3 – page 25 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

Instruction cycle based on FSMD model Fetch: IR <= databus; PC <= PC + 1; nextstate <= decode; . . . Execute_sub 1. . . Execute_add 1: accu<=accu + d 0; -- prepare fetch nextstate <= fetch; addressbus <= PC; Decode: case IR is when add: nextstate <= Execute_add 1; when sub: nextstate <= Execute_sub 1; when load: nextstate<= Execute_load 1; when store: nextstate <= Execute_store 1: end case; Computer Architecture – Part 3 – page 26 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

• To execute an instruction, it is loaded into the instruction register IR and decoded. The decoding is done by the FSM control unit (CU). • Decoding the instruction yields the control signals for the arithmetic logic units (ALU) in the datapath. • It furthermore selects up to three register – two for reading and one for writing (three-ported register file). • It also provides the write enable signals for the write operations • The ALU combines two operands, which are taken from the register file or from the instruction itself. Computer Architecture – Part 3 – page 27 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

• In case of a LOAD instruction, the ALU calculates the effective address. Then, the contents of the addressed memory cell is loaded into the register file. • On a STORE-Instruction the calculation of the effective address is also necessary. The operand to store must be made available at the same time. • Furthermore, the ALU generates flags (CC: condition codes), which can be evaluated by the control unit. • The program counter (PC) holds the address of the instruction to be executed next. It is normally incremented automatically (+). Computer Architecture – Part 3 – page 28 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

Instruction cycle of an existing sequential processor in pseudocode 1: forever { 2: 3: instr = prog [pc] 4: opcode 5: 6: a = data [source addr 1] b = data [source addr 2] 7: d = dest addr 8: +1 npc = pc + 1 case (opcode) { data memory instruction decoder ALU 9: 10: 11: 12: 13: 14: } 15: PC instruc -tion memory ADD: data [d] = a + b SUB: data [d] = a - b : BEQ: if (a == b) npc = d : pc = npc 16: } Computer Architecture – Part 3 – page 29 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

Multiplexer based 3 address Load-Store architecture for a CPU Computer Architecture – Part 3 – page 30 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

• The hardware cost of the Von-Neumann-principle is minimal. • It had its value in times when the hardware components were the biggest cost factor of a computer and optimal memory utilization was the most important design goal. • However, in the last three decades the cost situation has changed fundamentally due to the development of semiconductor technology. • As shown, particularly the connection between main memory and processor proves to be a bottleneck, as all data and instructions have to be transported by it. Computer Architecture – Part 3 – page 31 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

• Today, the processor’s instruction execution is significantly faster than the memory access, which even worsens the situation. • Processor techniques like instruction pipelining, superscalar principle, multithreading and multicores increased the data requirements considerably. Therefore, the pure Von-Neumann-Architecture principle is dropped in modern microprocessors. Cache-based Harvard-Architectures in combination with time and spatial parallelism can be found Computer Architecture – Part 3 – page 32 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

Classifications As seen, an instruction cycle consists of the part cycles: 1. instruction fetch 2. decode 3. instruction execute. In each instruction cycle at most one instruction is fetched from the main memory and then executed. This results in a sequential control flow. This computer class is called SISD: Single Instruction Single Data Computer Architecture – Part 3 – page 33 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

Flynn Classification SISD Single Instruction Single Data Von-Neumann SIMD Single Instruction Multiple Data Array- or Vectorprocessors, Multimedia Extensions MISD Multiple Instruction Single Data Fault-Tolerance (controversial) MIMD Multiple Instruction Multiple Data GRID, Cloud, Multicore, Computer Architecture – Part 3 – page 34 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

Classification by Control Unit There are basically two possible structures for the control unit: • direct (hardwired) control • micro programmed control The hardwired solution is mainly used in RISC designs whereas microprogramming is more common among CISC. The hardwired solution uses a FSM consisting of a hardwired combinatorial circuit to decode the instructions. This requires simple and regular instructions such as it is given by a RISC-ISA. Complex instructions, which are common in CISC, are interpreted using a micro programmed control. Computer Architecture – Part 3 – page 35 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

Hardwired control data hardwired control opcode; addr. etc. instruction register (IR) ALU complex combinatorial network state register control signals Computer Architecture – Part 3 – page 36 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

Processor (CPU) with hardwired control unit program control complex comb. network Functionalunit multiplexer status state register data register Computer Architecture – Part 3 – page 37 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

Implementation of a microprogrammed FSM next state vector control vector word lines Decoder xt bit lines zt+1 zt yt+1 register clock yt Computer Architecture – Part 3 – page 38 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

Adding the datapath to the microprogrammed FSM Instruction (program) control path microprogram memory decoder C state register C ALU control register next address operands ALU Computer Architecture – Part 3 – page 39 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt result data path Hier wird Wissen Wirklichkeit

Adding a sequencer to allow more comfortable microprogram operations Instruction (program) control path microprogram memory decoder C sequencer control C ALU control register Sequencer, µP counter operands ALU Computer Architecture – Part 3 – page 40 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt result data path Hier wird Wissen Wirklichkeit

Microprogrammed control data bus (micro) status information from ALU (FLAG) sequencer instruction opcode addr. etc. instruction register mapping ROM D µBZ start address micro instruction counter µPS microprogram micro program memory micro instruction register µIR address part control signals Computer Architecture – Part 3 – page 41 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

Processor (CPU) with micro programmed control unit program Sequencer control Micro program Functionalunit multiplexer status state register data register Computer Architecture – Part 3 – page 42 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

The most important parts of micro programmed instruction decoding are: • micro program memory (µPM) • “mapping”-ROM • micro instruction counter µBZ • micro instruction register µIR • sequencer IR is the instruction register that holds the current instruction to be executed. A decoder or “mapping”-ROM(D) maps opcodes to micro program address. The control unit interprets each instruction using a microprogram subroutine, which is stored in the micro program memory. Computer Architecture – Part 3 – page 43 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

A microprogram consists of a series of discrete microprogram instructions (micro instructions). When an instruction is executed, the sequence of micro instructions, whose start address is determined from the opcode, is processed. The start address is loaded into the µBZ. The addressed micro instruction is loaded into the micro instruction register. The micro program sequencer determines the address of the next micro instruction according to the control and address codes of the current one as well as the status flags of the ALU. This micro instruction is loaded into the micro instruction register. Selecting the next micro instruction and controlling the data path is done in parallel. Computer Architecture – Part 3 – page 44 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

Horizontal microprogramming is characterized by a direct mapping of the bits of the micro instruction onto the control signals (micro order). microprogram memory register. . . sequencer ALU control bus control Computer Architecture – Part 3 – page 45 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt fully parallel Hier wird Wissen Wirklichkeit

Quasi-horizontal microprogramming differs therein that each micro instruction is grouped in bit fields, which have to be decoded. microprogram memory register field select decoder. . . sequencer ALU control partly parallel bus control These fields may hold the address of the next micro instruction, the micro order for the ALU, numbers of registers or control signals for multiplexers. The associated decoders are usually part of the data path. The width of a microprogram word is shrinked while parallelism is reduced Computer Architecture – Part 3 – page 46 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

If the micro instructions are being decoded using firmware, this is called nanoprogramming. microprogram memory register field select nanoprogram memory partly sequential register. . . sequencer ALU control bus control Computer Architecture – Part 3 – page 47 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit

SISD computers are usually classified based on: • The number of separate paths for instructions and operands (Von. Neumann and Harvard architecture respectively) • The instruction set architecture (CISC/RISC) • The location, where operands are placed for processing: - memory-memory machine: The operands are loaded directly from the main memory. Fast registers as buffers for operands are abandoned. - virtual-register machine: A part of the main memory is used like a register file. - register-register or load/store machine: The operands have to be placed in registers before processing. This kind of architecture is going to be described in detail in the following. Computer Architecture – Part 3 – page 48 of 48 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hier wird Wissen Wirklichkeit