Codesign of Embedded Systems Allen C. -H. Wu Department of Computer Science Tsing Hua University Hsinchu, Taiwan, R. O. C {Email: chunghaw@cs. nthu. edu. tw}
Outline l Introduction l Implementation technologies l Design technologies l Summary Ref: Rolf Ernst, “Codesign of Embedded Systems: Status and Trends, IEEE Design and Test of Computers, pp. 45 -54, April-June, 1998.
Introduction Embedded systems: l Executes specific tasks within larger electronic device l Found in nearly everything electric - cars, office automation, PDA’s, home electronics, factory control Source: Dataquest Embedded IC revenues (B$)
Embedded system characteristics l Fixed functionality l I/O intensive, reactive l Multiple processes l Time constraints l Low cost ($8 -$100), low power (. 5 -4 W), small size
A typical embedded system structure SAP ASIP DSP Memory u. C u. P ASIC DSP Code I/O RTOS u. P Code D/A A/D
Implementation technologies (Processor types) l Micro-processor and micro-controller l ASIP - application-specific instruction-set processor l DSP - digital signal processor l SAP - single-application processor l ASIC - application-specific integrated circuit
Implementation technologies (Package types) l Full-custom IC l Cell-based IC l Gate array l PLD - FPGA l SOC (System-on-a-chip) - core-based design, Intellectual property (IP), system-level integration (merging hw/sw onto 1 chip)
Embedded-system design process Requirements definition Customer/ marketing Specification System architect Support (CAD, test) System architecture development SW development Interface design HW development Integration & test Source: Ernst (IEEE D & T of Computer) Reused comp.
Two types of codesign u. P/SAP-based design System Vertical partitioning Core processor Application-specific coprocessors SW HW
Two types of codesign ASIP-based design SW Application SW + simulator, compilers, OS System Vertical partitioning Application-specific processors HW
Design technologies l Design specification, modeling, and capture l Synthesis - system-level, RTL, logic level, physical level. l Design space exploration l Design verification and testing.
Specification and modeling l Executable specification - Verilog, VHDL, C, C++, Java. l Common models: synchronous dataflow (SDF), sequential programs (Prog. ), communicating sequential processes (CSP), object-oriented programming (OOP), FSMs, hierarchical/concurrent FSM (HCFSM). l Depending on the application domain and specification semantics, they are based on different models of computation.
Hardware Synthesis l Many RTL, logic level, physical level commercial CAD tools. l Some emerging high-level synthesis tools: the Behavioral Compiler (Synosys), Monet (Mentor Graphics), and Rapid. Path (DASYS). l Many open problems: memory optimization, parallel heterogeneous hardware architectures, programmable hardware synthesis and optimization, and communication optimization.
Software synthesis l The use of real-time operating systems (RTOSs) l The use of DSPs and micro-controllers - code generation issues l Special processor compilation in many cases is still far less efficient than manual code generation! l Retargeting issues - C code developed for the TI TMS 320 C 6 x is not optimized for running on Philips Tri. Media processor.
Software synthesis (Cont. ) l The porting is worse when using parallel compilers because of architecture specialization. l Using libraries of predefined and parameterized code modules adapted to an application: SPW and the Mentor Graphics DSP Station.
Interface synthesis l Interface between: - hardware-hardware - hardware-software - software-software l Timing and protocols l Has been neglected for a long time in commercial tools l Recently, first commercial tools appeared: the Co. Ware system (hw-sw protocols) and the Synopsys Protocol Compiler (hw interface synthesis tool)
Synthesis: status and trends l Many tools reach a high degree of automation for specific applications; however, many design tasks still need to be done manually l Lacking the ability of exploiting the design space to obtain an optimized solution l IP-based (core-based) synthesis methodology
Design space exploration l Process transformation l Hardware/software codesign tasks l Estimation l Manual/automated/assisted
Design space exploration process Customer/marketing system architect Cospecification High-level transformation System architect Design space exploration space System analysis Process transformation HW/SW partitioning and scheduling HW synthesis Reused functions and processes HW arch & comp. Reused HW & SW components SW synthesis Evaluation (cosimulation) Source: Ernst (IEEE D & T of Computer)
Process transformation l Communication transformation l Process merging l Granularity adaptation l Process retargeting : e. g. , a RISC -> a DSP
Granularity effects Granularity Process Function/ global data Optimization potential Analysis Communication overhead Design effort no(explicit) Global data flow Basic block/ local data set Global and local data flow Statement/ variables Global and local data flow
HW/SW codesign l Hardware-software partitioning l Communication synthesis l Hardware-software scheduling l Memory optimization l Estimation l Cosimulation
Communication synthesis l Communication channel selection l communication channel allocation l communication channel scheduling l Currently, no tool can cover the whole variety of communication mechanisms
HW/SW scheduling l Static scheduling l Derived from RTOSs - e. g. , static table-driven and priority-based preemptive scheduling l Static scheduling for event-driven reactive systems l Distributed scheduling policies for complex embedded architectures
Memory optimization l Dominant cost factor in integrated systems and the bottlenecks in system performance l Program cache optimization techniques l Optimization for architectures with memories of different types - such as scratch-pad SRAM and DRAM l Dynamic memory allocation
Estimation l Accuracy VS. fidelity l Simulation based l Fast synthesis based
Cosimulation l Simulate processor software along with custom hardware l Simulation speed, compile time, debugging capability, test vector creation l Speed VS. accuracy - rate accurate, functionally accurate, cycle accurate, gate accurate
Simulator categorization l General-purpose simulator - event-driven l Uni-purpose simulator - designed to simulate a specific model (e. g. , 80586) l Emulator - Logic emulator - Processor emulator - In-circuit emulator (ICE)
Common cosimulation approaches l HDL simulator l Simple to implement l Slow l Foreign software debug environment
Common cosimulation approaches l Linking software processor simulator and HDL simulator l Eagle-I (Mentor Graphics), Seamless (Viewlogic) l Ptolemy (UC Berkley) -- OO software framework for linking simulators l Faster, native software debug environment
Common cosimulation approaches l Linking processor emulator and logic emulator l Fast l In-circuit debugging l Expensive l Quickturn
Design verification and testing l Closely-coupled design, verification, and testing methodologies l Integrating multi-level design, verification, and testing design tasks l Cosimulation, coemulation, design for test l Rapid prototyping
Rapid prototyping l Custom-designed prototyping board l Logic emulators l Field-programmable PCBs
Development without prototyping SW Design Code Design Build Integration Debug Fab Debug
Development with prototyping SW Design Code System Integration & SW Debug HW Design CHIP Design Build HW Integration & Debug Chip debug Fab Final Integration
Summary l Embedded systems market is big and growing l Computer-aided hardware-software codesign has made considerable progress in the past few years l System analysis is in great demand cosimulation, coverification and cospecification l Cosynthesis and computer-aided design space exploration are just beginning to reach the industrial practice
Скачать презентацию Codesign of Embedded Systems Allen C -H Wu
c03a048707f15c9900b1a34cc8154848.ppt