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Characterization, Modeling and Optimization of Fills and Stress in Semiconductor Integrated Circuits Ph. D. Characterization, Modeling and Optimization of Fills and Stress in Semiconductor Integrated Circuits Ph. D. Defense Presentation Rasit Onur Topaloglu

Outline § § Introduction Chapter 2: Fill DOE (Design of Experiments) Chapter 3: Fill Outline § § Introduction Chapter 2: Fill DOE (Design of Experiments) Chapter 3: Fill Optimization Chapter 4: FEOL (Front End of the Line) Stress Modeling and Optimization § Chapter 5: BEOL (Back End of the Line) Stress Analysis and Guidelines § Chapter 6: Thermal Impact of Fills § Conclusions

Methodology Used in Thesis § Test structure design § Conduct TCAD (technology computer-aided design) Methodology Used in Thesis § Test structure design § Conduct TCAD (technology computer-aided design) simulations § Analyze results § Devise models when necessary § Provide design guidelines § Automate the process § Conduct circuit optimization

Integrated Circuit Stack and DFM Structures Contact fill (Poly) gate Poly fill M 1 Integrated Circuit Stack and DFM Structures Contact fill (Poly) gate Poly fill M 1 interconnect M 2 (CMP) fill Active (diffusion) Side view § § 1. 2. 3. Layout view Via 12 fill High yield manufacturability of an integrated circuit requires auxiliary DFM (design for manufacturability) structures Poly fills are used to enhance lithographic printability and variability enhancement CMP (chemical-mechanical polishing) fills are used for flat post-CMP topography of interconnects and dielectrics Via fills (a via between two CMP fills or an interconnect and a CMP fill) are used for improved via printability. We also use them for BEOL reliability enhancement Contact fills (a dummy contact) may be used for contact printability enhancement. We also use them for FEOL heat dissipation

The CMP Process § CMP is applied after metal deposition to smooth out the The CMP Process § CMP is applied after metal deposition to smooth out the most recent stack layer § Layer topography is at least a function of metal density and width in terms of layout parameters § Design manuals provide acceptable metal density ranges § Fills have to be inserted to make the density uniform § If not, CMP related problems slurry §Contains abrasives and chemicals Overremoval Puddling conditioner §A disk with diamond pyramids pad §Improves wafer removal rate Dishing Erosion Step height

Traditional CMP Fill Insertion § Layout filled stepping through fixed size windows § Fills Traditional CMP Fill Insertion § Layout filled stepping through fixed size windows § Fills are inserted as long as there is space § Fill size and spacing adjusted to yield a target density § Improvements exist that consider minimum density variation across windows or limit number of fill shapes Layout to be filled: § Addition of fills can be either handled by the design house (during design or at GDSout) or the foundry after GDSout § Ideally, fills should not alter the capacitances of and between interconnects. Design rules not sufficient to eliminate the impact of fills on capacitances: § for intralayer coupling : keep-off design rule used. Defines the minimum space between a fill and an interconnect. § for interlayer couplings : no design rule exists!

Outline Slide From Candidacy Presentation § Overview of Design for Manufacturability (DFM) for Interconnects Outline Slide From Candidacy Presentation § Overview of Design for Manufacturability (DFM) for Interconnects § Motivation § Known techniques § Open Issues § Targeted Problems § Problem 1: Design Rule Inferring § Problem 2: Interconnect Optimization § Problem 3: Probabilistic Simulation § Problem 4: Analyzing Effects of Fills § Problem 5: Metal Fill Optimization § Future Work § Problem 4 Extensions: Consideration of CMP § Problem 5 Extensions: Via-Fill Insertion § Problem 6: Performance-Driven Fill Insertion § Conclusions Although we have conference publications for Problems 1 -3, we focus on the blue items for thesis topic uniformity and depth.

The Fill Placement Problem § Given § A grid § A fill size § The Fill Placement Problem § Given § A grid § A fill size § Number of fills to be inserted for target fill density § Output Interconnect Coupling (F) § Optimal fill configuration which yields minimum intra and interlayer coupling 10% improvement Ideas were demonstrated on toy testcases

Outline § Introduction § Chapter 2: Fill DOE § A. B. Kahng and R. Outline § Introduction § Chapter 2: Fill DOE § A. B. Kahng and R. O. Topaloglu, “A DOE set for normalization-based extraction of fill impact on capacitances, ” Best Paper Award, Proc. IEEE International Symposium on Quality Electronic Design, 2007, pp. 467 -474. § A. B. Kahng and R. O. Topaloglu, “DOE-based extraction of CMP, active and via fill impact on capacitances, ” IEEE Trans. on Semiconductor Manufacturing, 21(1), 2008, pp. 22 -32. § § § Chapter 3: Fill Optimization Chapter 4: FEOL Stress Modeling and Optimization Chapter 5: BEOL Stress Analysis and Guidelines Chapter 6: Thermal Impact of Fills Conclusions

Motivation § Industry requires an accurate and compact DOE (design of experiments) set to Motivation § Industry requires an accurate and compact DOE (design of experiments) set to compare different fill options § Fill types : traditional, staggered, two-pass § Stack parameters: metal height, multiple interlayer dielectric stacks, different dielectric constants and heights § Design parameters: fill width, fill to fill spacing, keep-off distance, metal width, metal orientations § Impact of floating fills needs to be thoroughly analyzed to increase the understanding for optimal fill choice § RC extractors have known inaccuracies for floating fill extraction. A methodology is needed to: § accurately extract floating fill impact using the power of current extraction tools § without significantly changing the industry-standard extraction mechanism

Why RC Extractors Not Accurate? § Assuming Fills as Grounded: § Initial approximations were Why RC Extractors Not Accurate? § Assuming Fills as Grounded: § Initial approximations were based on this assumption § Although a fill is floating and not electrically connected, it is assumed to be grounded in this assumption § Assuming Fills as Merged: § Fills in the same layer are assumed to be merged using the convex hull of neighboring fills such that no interconnect is present in the hull § Another extension of merging fills is taking the fill density as the input to extraction § However, different fill patterns are known to have different couplings, especially for interlayer capacitances and even intralayer coupling when keep-off distance is small

Contribution 1: Compact DOE Structure § Use one compact structure to get multiple coupling Contribution 1: Compact DOE Structure § Use one compact structure to get multiple coupling capacitances § Use (Synopsys Raphael) field solver for 3 D accurate simulations B A A’ B’ Top (layout) view Side view along cutline 3 D view § A large structure would exponentially increase simulation time. § The main structure consists of 5 metal layers. Vertical layers are on layer M, horizontal lines are on layers M-1 and M+1 § Fills are inserted in layers M-1, M and M+1. M+2 and M-2 are ground planes § Using symmetric (Neumann) boundaries, intralayer (A-A’), first neighboring layer (A -B), and second neighboring layer (B-B’) coupling capacitances can be computed

Contribution 2: Integration of Proposed DOE § § RC extractions tools run DOEs for Contribution 2: Integration of Proposed DOE § § RC extractions tools run DOEs for regular interconnects. Users have access to the DOE parameters. Users do not have sufficient control over floating fill extraction RC extractors do pattern matching to find a pattern in layout similar to their DOE instances § § A similar pattern matching needs to be applied for floating fills. Proposed integration flow based on normalization: 1. Run DOE with and without fills. Record normalized cap. impact 2. Extract a layout with no fills first 3. Match layout pattern with a similar DOE structure 4. Multiply the extracted capacitances with normalized fill impact GDS with no fill GDS with fills

Contribution 3: DOE Algorithm and Parameters 1. foreach wf=wfmin: wfinc: wfmax { 2. foreach Contribution 3: DOE Algorithm and Parameters 1. foreach wf=wfmin: wfinc: wfmax { 2. foreach ws=wsmin: wsinc: wsmax { 3. foreach wm=wmmin: wminc: wmmax { 4. foreach cf=cfmin: cfinc: cfmax { 5. Run field solver over parameterized structure and add normalized results to the table. } } § Description of used parameters: § wm : metal width § wf : fill width § ws : fill spacing § cf : number of fill columns Metal width ( m) {0. 1, 0. 2, 0. 3, 0. 4} Fill width ( m) {0. 4, 0. 45, 0. 55} Fill spacing ( m) {0. 1, 0. 25, 0. 55} Fill shift (x) {0. 25, 0. 75, 1} Metal height ( m) {0. 3, 0. 4} Dielectric constant {3. 1, 2. 8} Number of fill columns {1, 2, 3} Keep-off distance ( m) {0. 3, 0. 5, 0. 7} Parameters for Staggered Fill Algorithm In addition to standard fill parameters Stagger Amount ( m) {0. 2, 0. 25, 0. 275} Number of fill columns {2, 3, 4} M, M Different fill algorithms accommodated Parameters for Two-pass Fill Algorithm In addition to standard fill parameters Two-pass ratio {2, 3}

Second Order Test Structures for DOE Impact of fills shift on 1 st and Second Order Test Structures for DOE Impact of fills shift on 1 st and 2 nd Impact of shift in neighboring layer coupling layer parallel lines M+1 M M-1 Top (layout) view § § § Side view Location of fills will impact M-1 to M+1 coupling as well as M-1 to M Shifting the fills on layer M, overlap between layer M+1 and M fills are reduced, which results in reduced coupling We introduce the shift factor as a parameter to evaluate the impact of fill shifts on coupling; shift factor is normalized with respect to the fill pitch § Fill shifts can alter neighboring layer orthogonal line coupling by up to 5%

Summary of Experimental Results STANDARD DOE Merged Grounded Max. Coupling/Total Min. Coupling/Total intra-layer 2. Summary of Experimental Results STANDARD DOE Merged Grounded Max. Coupling/Total Min. Coupling/Total intra-layer 2. 377 10. 336 0. 002 15. 91% 0% first-layer 1. 083 1. 123 0. 492 22. 25% 17. 11% second-layer 1. 126 0. 726 0. 094 6. 84% 2. 38% STAGGERED DOE Merged Grounded Max. Coupling/Total Min. Coupling/Total intra-layer 2. 579 25. 9308 0. 0021 23. 33% 0% first-layer 1. 131 1. 155 0. 578 20% 16. 32% second-layer 1. 153 0. 559 0. 107 6. 87% 0% 2 -PASS DOE Merged Grounded Max. Coupling/Total Min. Coupling/Total intra-layer 5. 308 34. 607 6. 00 E-06 3. 61% 0. 91% first-layer 1. 11 0. 531 0. 546 19. 56% 15. 91% 1. 016 0. 284 0. 147 7. 78% 3. 57% second-layer § Results normalized with respect to no-fill test structures, then averaged. § Merging fills results in up to 10 x overestimation for intralayer coupling for small keep-off distances § Grounding a fill results in § eliminating intralayer component to a large extent, § 2 x and 10 x underestimation of first and second layer coupling and § Standard fills can result in an average 2. 3 x intralayer, 8% and 12% first and second interlayer coupling increase

Summary of Contributions § An accurate and compact DOE set § An integration methodology Summary of Contributions § An accurate and compact DOE set § An integration methodology to accurately extract floating fill impact § using industry-standard extraction flow § utilizing normalization-based capacitance tables § Thorough analysis of floating fills § § Identification of important fill and design parameters Analysis of how each parameter affects the coupling capacitances A comparison of standard, staggered and two-pass fill algorithms Consideration of first and second neighboring layer interlayer coupling capacitances during the methodology § Provided this analysis capability to designers for them to conduct the experiments on their own technology and design

Outline § Introduction § Chapter 2: Fill DOE § Chapter 3: Fill Optimization § Outline § Introduction § Chapter 2: Fill DOE § Chapter 3: Fill Optimization § R. O. Topaloglu, “Energy-minimization model for fill synthesis, ” Proc. IEEE International Symposium on Quality Electronic Design, 2007, pp. 444 -451. § A. B. Kahng and R. O. Topaloglu, “Performance-aware CMP fill pattern optimization, ” Invited Paper, Proc. International VLSI/ULSI Multilevel Interconnection Conference (VMIC), 2007, pp. 135 -144. § A. B. Kahng and R. O. Topaloglu, “Performance-oriented interlayer-aware CMP fill pattern optimization, ” under review in IEEE Trans. on Computer-Aided Design, 2008. § § Chapter 4: FEOL Stress Modeling and Optimization Chapter 5: BEOL Stress Analysis and Guidelines Chapter 6: Thermal Impact of Fills Conclusions

Motivation § Classical fill synthesis methods focus on density uniformity only. Impact on circuit Motivation § Classical fill synthesis methods focus on density uniformity only. Impact on circuit performance minimally considered § Fill insertion guidelines exist but currently no way is known to automate them §Place fills to form a hourglass shape §Place fills away from interconnects. §A path to facilitate parallel flux flow is generated §Minimize number of fills close to interconnects § Manual application of guidelines is not feasible for large designs. Need automation § Need account for circuit timing in fill insertion § Need account for interlayer coupling impact on timing § Optimization should target to gain back the capacitance increase introduced by timing-unaware (traditional) fills. Regain back at least 50% timing slack lost due to fills § Need power-aware fill for power-critical circuits

Adaptive Region Definition § We use region-based fill insertion § Maximum width empty regions Adaptive Region Definition § We use region-based fill insertion § Maximum width empty regions identified between facing interconnects using scanline algorithm Interconnect Region Grid rectangle Keepoff distance § After stripping out keep-off distances, a grid holding possible fill locations is formed § If orthogonal interconnect segments exist, we disable overlapping grid rectangle locations

Contribution 1: The Grid Model Utilizing Bonds § In this example, there are 36 Contribution 1: The Grid Model Utilizing Bonds § In this example, there are 36 rectangles with two fills in the grid shown below Region Grid rectangle Bonds incident to a location Interconnect Keep-off distance Fill Vertical bond Auxiliary frame Horizontal bond § An auxiliary frame is formed holding grid rectangles with bonds in between § Each bond has an adjustable energy. (During development, inspired by physical analogy of electrons filling orbits of an atom) § When inserting a fill, bonds incident to a rectangle are summed up to find an energy; we find minimum energy location to insert a fill

Contribution 2: Energy Modeling in a Grid § Modeling of bonds indicates which location Contribution 2: Energy Modeling in a Grid § Modeling of bonds indicates which location should be filled with higher priority § Model is flexible enough to satisfy target guidelines § Adjustable four-parameter model for vertical and horizontal bonds § Although we use linear models, second-order and more complex models can also be used Vertical model: Y Horizontal model: i : enumeration for a row of grid rectangle locations j : enumeration for a column of grid rectangle locations imid : middle row number Energies for vertical bonds jmid : middle column number , , , : fitting parameters X § Z axis gives the bond energy. Energies for horizontal bonds

Experimental Setup and Protocol § Cadence SOC Encounter v 5. 2 used for placement Experimental Setup and Protocol § Cadence SOC Encounter v 5. 2 used for placement and clock tree synthesis and Nano. Route used for routing § Synopsys Star. RCXT 2006. 06 used for RC extraction § We use C++ code for proposed fill insertion methodology MFO (Metal Fill Optimizer). We compare against best available industry tools for the purpose: Mentor Calibre and Blaze IF § We use TSMC 65 nm GPlus library § S 38417, AES, ALU and an industrial testcase § Compare impact of fill algorithm on timing and power Fill Design Rules from Library Exchange File Sizes for Traditional Fill

Contribution 3: Interlayer-Aware Fill Synthesis Flow 1. Place, synthesize clock network and route design Contribution 3: Interlayer-Aware Fill Synthesis Flow 1. Place, synthesize clock network and route design 2. Extract SPEF parasitics from DEF 3. Run static timing analysis using SPEF file from Step 2 4. Use Perl scripts to obtain top critical net names 5. Check critical nets on neighboring layers for each net 6. Update energy values for bonds 7. Insert interlayer-aware fills §Add vertical bonds Slack Comparison

Power-Aware Fill § We alter the flow for interconnect switching power criticality 1. 2. Power-Aware Fill § We alter the flow for interconnect switching power criticality 1. 2. 3. 4. 5. 6. 7. Place, synthesize clock network and route design Extract SPEF parasitics from DEF Compute interconnect switching power using SPEF file from Step 2 Use Perl scripts to obtain top power-critical net names Check critical nets on neighboring layers for each net Update energy values for bonds Insert power-aware fills

Discussion of Results §Timing slacks shown §Less negative (towards the right) is better §Proposed Discussion of Results §Timing slacks shown §Less negative (towards the right) is better §Proposed Metal Fill Optimizer (MFO) outperforms intelligent fill (IF) variations

Post-Fill Copper Height Topographies and Histograms §Core 1 of industrial testcase Traditional fill §We Post-Fill Copper Height Topographies and Histograms §Core 1 of industrial testcase Traditional fill §We obtain a histogram with a single peak MFO fill

Conclusions and Contributions § § § § Physically-motivated heuristic Testbed with 65 nm Gplus Conclusions and Contributions § § § § Physically-motivated heuristic Testbed with 65 nm Gplus process and fill design rules Complex fill insertion guidelines are automated Large testcases including an industrial testcase Interlayer layout awareness utilized for the first time Timing-aware fill implemented Power-aware fill option It is possible to reduce the fill impact on timing § by up to 85% for 30% pattern density and § by up to 65% for 60% pattern density.

Outline § § Introduction Chapter 2: Fill DOE Chapter 3: Fill Optimization Chapter 4: Outline § § Introduction Chapter 2: Fill DOE Chapter 3: Fill Optimization Chapter 4: FEOL Stress Modeling and Optimization § R. O. Topaloglu, “Standard cell and custom circuit optimization using dummy diffusions through STI width stress effect utilization, ” Proc. IEEE Custom Integrated Circuits Conference, 2007, pp. 619 -622. § A. B. Kahng, P. Sharma and R. O. Topaloglu, “Exploiting STI stress for performance, ” Proc. IEEE/ACM International Conference on Computer-Aided Design, 2007, pp. 83 -90. § A. B. Kahng, P. Sharma and R. O. Topaloglu, “Chip optimization through STI stress-aware placement perturbations and fill insertion, ” accepted for publication in IEEE Trans. on Computer-Aided Design, 2008. § Chapter 5: BEOL Stress Analysis and Guidelines § Chapter 6: Thermal Impact of Fills § Conclusions

Introduction to STI § STI (Shallow Trench Isolation) is used to isolate devices from Introduction to STI § STI (Shallow Trench Isolation) is used to isolate devices from each other. § (NMOS from NMOS, NMOS from PMOS, etc. ) § Diffusion fills traditionally used for flat STI-diffusion topography. In this thesis, we also use them for stress optimization LAYOUT VIEW SIDE VIEW ALONG CUTLINE N-type device Standard cell STI P-type device P-type active (diffusion) fill N-type active (diffusion) fill Filler cell

Introduction to Stress Engineering §Stress engineering methods utilized starting 65 nm are § § Introduction to Stress Engineering §Stress engineering methods utilized starting 65 nm are § § § Si. Ge stress from underneath the channel, embedded Si. Ge from the source and drain, dual stress liner new technology, needs analysis/optimization stress memorization and hybrid orientation [PMOS on (110) NMOS on (100)] §(Compressive) stress (along the channel) § improves PMOS speed by increasing mobility and § degrades NMOS speed by decreasing mobility. §STI (Shallow Trench Isolation) exerts compressive stress. §Stress can also be utilized to improve performance. We need models for analysis and circuit level optimization § Need >5% speed improvement

Background on STI Width Stress Effect §STI stress modeled as dependent on SA and Background on STI Width Stress Effect §STI stress modeled as dependent on SA and SB only in BSIM (4. 6. 1). § STI width (STIW) effect not modeled § A larger STIW implies a larger stress 3 2 1 NOT MODELED No models are provided. Need models for circuit analysis [ H. Tsuno et al. , 2007 Symp. on VLSI ]

STI Width Simulations § We conduct 2 D TCAD simulations to evaluate the impact STI Width Simulations § We conduct 2 D TCAD simulations to evaluate the impact of STIW stress on channel mobility § We use Synopsys Sentaurus for simulations § We simulate a DOE. We change SA, SB and STIWleft and STIWright § MOB in the figure is the normalized mobility § As LOD is reduced and/or STIW is increased along channel direction § PMOS mobility increases; NMOS mobility decreases (along channel) PMOS NMOS

Contribution 1: STIW Models and Layout Extraction NMOS §STI stress models: PMOS STIW L Contribution 1: STIW Models and Layout Extraction NMOS §STI stress models: PMOS STIW L SA STIW R SB §Each device in a cell affected differently §Layout parameter extraction * Critical path 0001 X 01 N 2 INVX 1 PL=0. 08 u PR=4. 08 u NL=0. 06 u NR=4. 06 u X 02 N 2 1 N 3 NAND 2 X 1 PL=5. 0 u PR=5. 0 NL=5. 0 u NR=5. 0 u X 03 N 4 BUFFX 1 PL=2. 1 u PR=5. 0 u NL=2. 04 u NR=5. 0 u : : . subckt INVX 1 A Z MM 1 D G S B NCH SA=0. 2 u SB=0. 2 u MOB=STIW_P_MODEL(PL, PR, NL, NR, SA, SB) MM 2 D G S B NCH SA=0. 19 u SB=0. 19 u MOB=STIW_N_MODEL(PL, PR, NL, NR, SA, SB) : . ends X, Y : from placement W, Z: from cell layout SA, SB: from cell layout Already used in BSIM stress modeling and available

Contribution 2: STI Stress Optimization for Timing § Goal: engineer STIW such that stress Contribution 2: STI Stress Optimization for Timing § Goal: engineer STIW such that stress speeds PMOS and NMOS § Knobs to alter STIW § Active layer fill insertion § Fill inserted next to NMOS Small STIW for NMOS § Placement perturbation § Increase space for active layer fill insertion Don’t Touch Cell Timing Critical Cells Before Optimization After Placement Perturbation After Placement and Fill Optimization § Minimize adverse timing impact of placement perturbation. § Don’t modify locations of critical cells, their routes, clock tree, and flip-flops

Experimental Setup § 65 nm high-performance process § SP&R using Synopsys Design Compiler and Experimental Setup § 65 nm high-performance process § SP&R using Synopsys Design Compiler and Cadence So. C Encounter § RC Extraction using So. C Encounter § Synopsys HSPICE for SPICE simulation § Testcases: § Overall flow: § Identify critical paths and critical cells § Perform placement perturbation optimization § Perform active fill insertion § Perform ECO routing followed by parasitic extraction § Evaluate the optimized layout with STI stress-aware timing analysis

Results: Optimization § 4. 37% average reduction in minimum cycle time (MCT) § 5. Results: Optimization § 4. 37% average reduction in minimum cycle time (MCT) § 5. 15% average reduction in total path delay (TPD) Path delay histogram for AES §Negligible wirelength increase (<0. 67%) §Smaller delay reduction for s 38417 because >50% cells are flops and marked don’t-touch

Results : Full-Custom Optimization § With standard cell designs, we placed diffusion fills only Results : Full-Custom Optimization § With standard cell designs, we placed diffusion fills only outside the cells § There may be unutilized spaced inside the cells. § A full custom optimization on a standard cell 33 -stage MSRO fanout 2 with NAND, NOR, OAI and MUX results in 9% improvement Impact of Diffusion Fill on RC § Dense M 1 layer with M 2 on top § Case 1: underlying grounded diffusion § Case 2: no underlying layer § Case 3: underlying diffusion fill M 1 ~2. 5%

Dual Stress Liner § § § Compressive liner over PMOS, tensile liner over NMOS Dual Stress Liner § § § Compressive liner over PMOS, tensile liner over NMOS Speed improves for both (15 -30+ %) The proximity of opposite stress liner may alter the improvement Additional 5 -10% improvement or degradation possible due to opposite liner Need test structures and guidelines for characterization and optimization We use Synopsys FAMMOS for simulations

Contribution 3: DSL Stress Analysis and Guidelines X y 1. 2. 3. 4. Place Contribution 3: DSL Stress Analysis and Guidelines X y 1. 2. 3. 4. Place tensile liner away from PMOS in the parallel direction Place tensile liner close to PMOS in the orthogonal direction Place compressive liner away from NMOS in the parallel direction Place compressive liner away from NMOS in the orthogonal

Contributions § Performed TCAD process simulations to develop STI width compact models for STI Contributions § Performed TCAD process simulations to develop STI width compact models for STI width effect § Proposed a SPICE-based timing analysis flow that uses the compact models to model stress § Circuit-level stress optimization using placement perturbation and active fill insertion to improve timing § 4. 37% and 5. 15% improvements in MCT and TPD respectively § Analyzed DSL technology and provided design guidelines

Outline § § § Introduction Chapter 2: Fill DOE Chapter 3: Fill Optimization Chapter Outline § § § Introduction Chapter 2: Fill DOE Chapter 3: Fill Optimization Chapter 4: FEOL Stress Modeling and Optimization Chapter 5: BEOL Stress Analysis and Guidelines § A. B. Kahng and R. O. Topaloglu, “A TCAD-based study of fill pattern and via fill impact on low-k dielectric stress, ” Invited Paper, Proc. International Chemical. Mechanical Polishing for ULSI Multilevel Interconnection Conference (CMPMIC), 2007, pp. 337 -346. § Chapter 6: Thermal Impact of Fills § Conclusions

Motivation § § Fill pattern and location alter the interconnect and dielectric stress due Motivation § § Fill pattern and location alter the interconnect and dielectric stress due to the interconnect manufacturing process steps The stress due to fills can in turn alter the reliability Designers need thorough analyses and guidelines for proper insertion of fills to optimize reliability Stress cannot be directly measured but inferred through strain and elastic properties. Local changes would not be feasible to monitor in silicon, hence we prefer TCAD 1. 2. 3. 4. Need test structures to evaluate impact of fills Need relate stress type and location to BEOL reliability Evaluate whether via fills can be used to improve reliability Need provide design guidelines for fill insertion for reliability

Stress Computations for BEOL § The stress vector Tx acting normal to x is Stress Computations for BEOL § The stress vector Tx acting normal to x is given in [1] as § In this equation, § ij are shear components directed towards j on the orthogonal face to i, § ii’s are stress components normal to the unit cube faces; used for analyzing the impact of stress von Mises stress average stress [1] H. A. Rueda, “Modeling of Mechanical Stress in Silicon Isolation Technology and Its Influence on Device Characteristics, ” Ph. D. Thesis, 1999.

Impact of Mechanical Stress on Reliability § Stress Migration or Stress Induced Voiding: § Impact of Mechanical Stress on Reliability § Stress Migration or Stress Induced Voiding: § Stress migration results in metal voids. § The main causes of the stress gradients are the development of tensile stresses over thermal cycles due to manufacturing and accompanying thermal mismatches, etch and deposition steps § Reduction of stress gradients results in improved stress migration § Dielectric Breakdown: § There have been works in the literature showing the impact of stress on time dependent dielectric breakdown for gate dielectrics § Following a similar reasoning, it is also expected that stress would influence the characteristics for low-k dielectrics. § Stress components normal to material boundaries can result in crack starts and delamination § Reducing the stress would help to reduce the delamination. low-k § Copper Diffusion into Low-k: cap layer liner (Ta) § Stress components can alter the material boundaries which could increase the possibility of copper ion diffusion into low-k

Contribution 1: Test Structures for Fill Impact on Reliability Fill pattern Fill location between Contribution 1: Test Structures for Fill Impact on Reliability Fill pattern Fill location between orthogonal lines 2 nd neighboring layer parallel lines M 1, M 2, M 3 Via Fill Impact M 1, M 2, M 3, V 23 M 1, M 2, V 12 M 1, M 2, M 3 BEOL Reliability Improvement (BRI) M 1, M 2, M 3, V 23

Simulation Setup § In our simulations, we have used up to 3 metal layers, Simulation Setup § In our simulations, we have used up to 3 metal layers, all having the same minimum width, nominal metal height and via sizes § We have used the dual-damascene flow below. We have provided the steps per a single via and trench § The simulator (Synopsys FAMMOS) accounts for the stress changes due to deposition and thermal mismatches § We have taken a deposition temperature of 250 o. C. If the process has a higher deposition temperature, the stress change due to thermal mismatch will be higher

Contribution 2: Stress Measurement Points § It is important where you measure stress § Contribution 2: Stress Measurement Points § It is important where you measure stress § Ellipses indicate locations of interest to understand the impact due to stress. Multiple materials meet in these locations, making them significant for reliability § Reliability concerns such as Cu+ diffusion into dielectric and crack formation are highly prone to the imperfections in these regions § Use von Mises stress at m 2 § Stress difference along the interconnect should help us to understand the impact on stress migration. Stress in the interconnect center would also help § Use average stress at m 1 § The measurement inside the dielectric should be helpful to monitor the dielectric breakdown reliability. § Use average stress at m 3 § The difference in the normal component close to the top boundary gives information about the delamination and copper diffusion reliability § Use m 1 – m 4 orthogonal stress difference m 4 x xx x m 3 m 1 m 2

Contribution 3: Conclusions and Proposed Design Guidelines 1. 2. 3. 4. Above 20% Impact: Contribution 3: Conclusions and Proposed Design Guidelines 1. 2. 3. 4. Above 20% Impact: Reduce process temperature to improve reliability Insert BRI via fills to connect interconnects to neighboring layer fills to reduce delamination and crack starts Insert a fill between second neighboring parallel lines to decrease the delamination and crack formation possibility 8 -20% Impact: Insert fill near orthogonal or parallel lines on neighboring layers to reduce stress migration Increase aspect ratio to decrease Cu+ diffusion possibility Decrease aspect ratio to decrease the delamination and crack formation possibility Reduce fill size to reduce delamination

Outline § § § § Introduction Chapter 2: Fill DOE Chapter 3: Fill Optimization Outline § § § § Introduction Chapter 2: Fill DOE Chapter 3: Fill Optimization Chapter 4: FEOL Stress Modeling and Optimization Chapter 5: BEOL Stress Analysis and Guidelines Chapter 6: Thermal Impact of Fills Conclusions

Introduction to Device Thermal Effects § Device heating § reduces performance by reducing drive Introduction to Device Thermal Effects § Device heating § reduces performance by reducing drive current and § increases leakage exponentially dependent on temperature § Each material has a coefficient of thermal conductivity (CTC) § Oxides cannot conduct heat well; polysilicon has mid-range CTC and metals have high CTCs § We can increase the volume of structures with high CTC connected to the device to reduce device temperature § Layout-based improvements should be utilized whenever possible § It would be difficult to probe local layout change impact on temperature, hence a TCAD-based analysis is preferable § Need design test structures to evaluate fill impact on device heating § Evaluate whether contact fills and via fills help heat dissipation § Provide design guidelines

Contribution 1: Test Structures for Fill Thermal Impact Contact fill Contact Gate Via 12 Contribution 1: Test Structures for Fill Thermal Impact Contact fill Contact Gate Via 12 fill M 1 M 2 § We evaluate the impact of via and contact fills on device heating. We introduce the idea of using contact and via fills for device temperature reduction

Contribution 2: Experiments and Design Guidelines Experimental Setup. § Synopsys Raphael field solver § Contribution 2: Experiments and Design Guidelines Experimental Setup. § Synopsys Raphael field solver § Reflective boundary conditions § A heat sink of 25 o. C at the bottom of substrate. 30 nm region under channel assumed to produce 0. 25 W/µm 3 heat Guidelines. 1. Drawing interconnects over a device does not improve temperature. Device channel needs to be connected to other structures to reduce temperature 2. Enlarge active area whenever possible 3. Insert via fills to connect M 1 interconnects to M 2 fills 4. Insert contact fills to connect diffusion layer to M 1 fills if active area is large 5. Insert contact fills alone if not possible to connect to M 1 fills Using guidelines, device temperature can be reduced by 2. 5 to 5 o. C 5+% leakage reduction

Outline § § § § Introduction Chapter 2: Fill DOE Chapter 3: Fill Optimization Outline § § § § Introduction Chapter 2: Fill DOE Chapter 3: Fill Optimization Chapter 4: FEOL Stress Modeling and Optimization Chapter 5: BEOL Stress Analysis and Guidelines Chapter 6: Thermal Impact of Fills Conclusions

Conclusions – What is Ahead (Based on research directions from IEDM 07, IRPS 07 Conclusions – What is Ahead (Based on research directions from IEDM 07, IRPS 07 and ITC 08) § At 22 nm, new device structures § Fin. FET, III-V based devices or germanium channel devices. § Stress and liners still utilized to improve stress § Device heating will be of high importance. Layout-based thermal analyses and optimizations will be required § BEOL § Low-k below dielectric constant of 2. 0 Stability and reliability analyses required § Air gap interconnects Layout-based stress analysis in addition to electrical performance impact may be mandatory § Packaging: Through silicon vias, stacked chip configurations Will require layout-based stress analysis and optimization § Techniques proposed in this thesis seems to be sufficient for 45 nm design and such methods with modifications will be used down to 22 nm

Ph. D. Timeline – Pre-Ph. D. Work “You are what you publish. ” 1. Ph. D. Timeline – Pre-Ph. D. Work “You are what you publish. ” 1. R. O. Topaloglu, H. Kuntman and O. Cicekoglu, “Novel notch and bandpass filter structures using OTAs and OPAMPs, ” Proc. International Conference on Electrical and Electronics Engineering, pp. 63 -67, 2001. 2. E. S. Erdogan, R. O. Topaloglu, O. Cicekoglu and H. Kuntman, “New current-mode special function continuous time active filters employing only OTAs and OPAMPs, ” International Journal of Electronics, 91(6), 2003, pp. 345359. 3. R. O. Topaloglu, H. Kuntman and O. Cicekoglu, “Current-input current-output notch and bandpass analog filter structures as alternatives to active-R circuits, ” Frequenz, 57(5 -6), 2003, pp. 123 -127. 4. E. S. Erdogan, R. O. Topaloglu, O. Cicekoglu, H. Kuntman and A. Morgul, “Novel multiple function analog filter structures and a dual-mode multifunction filter, ” International Journal of Electronics, 93(9), 2006, pp. 637 -650, DOI: 10. 1080/00207210600711713. Listed as number 5 in 2006 most downloaded articles.

Ph. D. Timeline – Initial Stages Funding through SRC projects 5. R. O. Topaloglu Ph. D. Timeline – Initial Stages Funding through SRC projects 5. R. O. Topaloglu and A. Orailoglu, “On mismatch in the deep sub-micron era - from physics to circuits, ” Proc. Asia and South Pacific Design Automation Conference, 2004, pp. 62 -67. 6. R. O. Topaloglu and A. Orailoglu, “Forward discrete probability propagation method for device performance characterization under process variations, ” Proc. Asia and South Pacific Design Automation Conference, 2005, pp. 220 -223. 7. R. O. Topaloglu and A. Orailoglu, “A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs, ” Proc. IEEE/ACM/EDAC Design Automation Conference, 2005, pp. 851 -856.

Ph. D. Timeline – Transition Period ~6 months on my own Qualcomm and AMD Ph. D. Timeline – Transition Period ~6 months on my own Qualcomm and AMD internships for support 8. R. O. Topaloglu, “Process variation-aware multiple-fault diagnosis of thermometercoded current-steering DACs, ” IEEE Trans. on Circuits and Systems. II: Analog and Digital Signal Processing, 54(2), 2007, pp. 191 -195. 2006. 9. R. O. Topaloglu, “Monte Carlo-alternative probabilistic simulations for analog systems, ” Proc. IEEE International Symposium on Quality Electronic Design, 2006, pp. 249 -253. 10. R. O. Topaloglu, “Early, accurate and fast yield estimation through Monte Carloalternative probabilistic behavioral analog system simulations, ” Proc. IEEE VLSI Test Symposium, 2006, pp. 136 -142. 11. V. Wason, J. X. An, J. -S. Goo, Z. -Y. Wu, Q. Chen, C. Thuruthiyil, R. Topaloglu, P. Chiney and A. Icel, “Statistical compact modeling and Si verification methodology, ” Invited Paper, Proc. International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), 2006, pp. 1198 -1201.

Ph. D. Timeline – Under Prof. Kahng’s Guidance GSRC and STARC projects for support Ph. D. Timeline – Under Prof. Kahng’s Guidance GSRC and STARC projects for support 12. A. B. Kahng and R. O. Topaloglu, “Generation of design guarantees for interconnect matching”, Proc. IEEE/ACM System Level Interconnect Prediction Workshop, 2006, pp. 2934. 13. A. B. Kahng and R. O. Topaloglu, “Interconnect matching design rule inferring and optimization through correlation extraction, ” Proc. IEEE International Conference on Computer Design, 2006, pp. 222 -229. joined AMD 14. A. B. Kahng and R. O. Topaloglu, “A TCAD-based study of fill pattern and via fill impact on low-k dielectric stress, ” Invited Paper, Proc. International Chemical-Mechanical Polishing for ULSI Multilevel Interconnection Conference (CMP-MIC), 2007, pp. 337 -346. 15. A. B. Kahng and R. O. Topaloglu, “A DOE set for normalization-based extraction of fill impact on capacitances, ” Best Paper Award, Proc. IEEE International Symposium on Quality Electronic Design, 2007, pp. 467 -474. 16. A. B. Kahng, P. Sharma and R. O. Topaloglu, “Exploiting STI stress for performance, ” Proc. IEEE/ACM International Conference on Computer-Aided Design, 2007, pp. 83 -90. 17. A. B. Kahng and R. O. Topaloglu, “Performance-aware CMP fill pattern optimization, ” Invited Paper, Proc. International VLSI/ULSI Multilevel Interconnection Conference (VMIC), 2007, pp. 135 -144. 18. A. B. Kahng and R. O. Topaloglu, “DOE-based extraction of CMP, active and via fill impact on capacitances, ” IEEE Trans. on Semiconductor Manufacturing, 21(1), 2008, pp. 22 -32. 19. A. B. Kahng, P. Sharma and R. O. Topaloglu, “Chip optimization through STI stress-aware placement perturbations and fill insertion, ” accepted for publication in IEEE Trans. on Computer-Aided Design, 2008. 20. A. B. Kahng and R. O. Topaloglu, “Performance-oriented interlayer-aware CMP fill pattern optimization, ” under review in IEEE Trans. on Computer-Aided Design, 2008.

Ph. D. Timeline – Final Stages/AMD Work AMD funding for support 21. R. O. Ph. D. Timeline – Final Stages/AMD Work AMD funding for support 21. R. O. Topaloglu, “Via chamfering modeling for improved MIM capacitance silicon correlation, ” Proc. International VLSI/ULSI Multilevel Interconnection Conference (VMIC), 2007, pp. 362 -364. 22. R. O. Topaloglu, “Standard cell and custom circuit optimization using dummy diffusions through STI width stress effect utilization, ” Proc. IEEE Custom Integrated Circuits Conference, 2007, pp. 619 -622. 23. R. O. Topaloglu, “Energy-minimization model for fill synthesis, ” Proc. IEEE International Symposium on Quality Electronic Design, 2007, pp. 444 -451. 24. R. O. Topaloglu, “Process variation characterization and modeling of nanoparticle interconnects for foldable electronics, ” Proc. IEEE International Symposium on Quality Electronic Design, 2008, pp. 498 -501.

Ph. D. Timeline – Future Outlook § During Ph. D. , have § § Ph. D. Timeline – Future Outlook § During Ph. D. , have § § § § § helped with reviews at top conferences (ICCAD, DAC, …) reviewed journals (Trans. on VLSI, IET Circuits Devices and Systems) helped review NSF proposals helped write SRC proposals (1 got accepted for 3 year support of 2 students that I know of. ) mentored SRC projects (currently, liaison for 4 projects) worked at National Semiconductor, Qualcomm, AMD written patents (4 pending and 4 in pipeline, applied through AMD) worked as Technology and Integration Engineer II in Compact Modeling and Characterization Group at AMD received § AMD Technology Development Group Technical Achievement Award § AMD Author of Merit Award § Plans after Ph. D. § continue at AMD 2 -3 more years, be Member of Technical Staff, § publish more along the leads I have identified (silicon STI test structures and silicon BRI test structures), § increase mentorship involvement with SRC projects and § go back to academia as an assistant professor.

Thank You § Thank you! § Questions? Thank You § Thank you! § Questions?