CENG 450 Computer Systems Architecture Lecture 1

CENG 450 Computer Systems & Architecture Lecture 1 Amirali Baniasadi amirali@ece. uvic. ca

CENG 450: Computer Architecture Instructor: Amirali Baniasadi EOW 441, Only by appt. Call or email with your schedule. Email: amirali@ece. uvic. ca Office Tel: 721 -8613 Web Page for this class will be at http: //www. ece. uvic. ca/~amirali/courses/ceng 450. html Text: Computer Architecture A Quantitative Approach Filth edition, by Patterson and Hennessy Lecture notes will be posted on the course web page in advance. 2

Course Structure z Lectures: y 1 week on Overview and Introduction (Chap 1) y 2 weeks on ISA Design (Chap 2) y 6 weeks on Proc. Design (Chap 3 , 4) y 4 weeks on Memory and I/O (Chap 5) z Reading assignments posted on the web for each week. z NO Homework: Problems will be posted on the web site so you can prepare for exams/quizzes. z Quizzes: 4 in class quizzes. Dates will be announced in advance. z Note that the above is approximate. 3

Course Philosophy z Book to be used as supplement for lectures (If a topic is not covered in the class, or a detail not presented in the class, that means I expect you to read on your own to learn those details) z One Project (25%) z Four Quizzes (25%)- Will be announced in advance. z Final Exam(50%) z IMPORTANT NOTE: Must get passing grade in all components to pass the course. Failing any of the three components will result in failing the course. 4

Project z Labs start at Week of Jan 23 rd. z Processor design. 5

Topics z z z z Computer Architecture? History Technology Moore’s law & Virtuous circle Language evolution Components of a computer Instruction set architecture (ISA) 6

How many “computers” do you have? z Three different computing markets: 1. Desktop Computing: low-end systems, high performance workstations. Price $500 to $5000 2. Servers: web servers. Should be available and reliable. Availability: be ready if components fail. Scalability: ability to grow 3. Embedded computers: Hidden computers, ex. cell phones, washing machine, palmtop, watch… Minimize memory and power. Often not programmable. 7

What is “Computer Architecture” Computer Architecture: Behind the doors! Computer Architecture = Instruction Set Architecture + Machine Organization + Hardware Instruction Set Architecture: Visible to Compiler. RISC vs. CISC. Machine Organization: Importance of Von Newman design. 8

ISA z 1950 s: Hardwired Control, easy to implement, limited resources z 1960 s: Microprogramming, more flexibility. z 1970 s: CISC: l Compilers in infancy so ISA designed for programmers. l Expensive & small memory: Highly encoded, Multiple size instructions (e. g. , x 86 from 1 -17 bytes), ISA approximates high level languages, z 1980 s: RISC: l Better compiler, cheaper memory, “elemental instructions” z 2000 s: More resources, post-RISC? CISC: ”walk-across-the-room-without-stepping-on-the-dog” RISC: ”walk-walk-step over dog-walk” 9

History 1. “Big Iron” Computers: Used vacuum tubes, electric relays and bulk magnetic storage devices. No microprocessors. No memory. Example: ENIAC (1945), IBM Mark 1 (1944) 10

History Von Newmann: Invented EDSAC (1949). First Stored Program Computer. Uses Memory. Importance: We are still using the same basic design. 11

Computer Components Output Processor Control (CPU) Memory Input Printer Screen Disk. . . keyboard Mouse Disk . . . 12

Computer Components z Datapath of a von Newman machine OP 1 + OP 2. . . Op 1 Op 2 Bus Op 1 General-purpose Registers Op 2 ALU i/p registers ALU OP 1 + OP 2 ALU o/p register 13

Computer Components z Processor(CPU): y Active part of the motherboard y Performs calculations & activates devices y Gets instruction & data from memory y Components are connected via Buses z Bus: y Collection of parallel wires y Transmits data, instructions, or control signals z Motherboard y Physical chips for I/O connections, memory, & CPU 14

Computer Components z CPU consists of y Datapath (ALU+ Registers): x Performs arithmetic & logical operations y Control (CU): x Controls the data path, memory, & I/O devices x Sends signals that determine operations of datapath, memory, input & output 15

Technology Change z Technology changes rapidly y HW x. Vacuum tubes: Electron emitting devices x Transistors: On-off switches controlled by electricity x. Integrated Circuits( IC/ Chips): Combines thousands of transistors x. Very Large-Scale Integration( VLSI): Combines millions of transistors x. What next? y SW x. Machine language: Zeros and ones x. Assembly language: Mnemonics x. High-Level Languages: English-like x. Artificial Intelligence languages: Functions & logic predicates x. Object-Oriented Programming: Objects & operations on objects 16

Moore’s Prediction 17

Moore’s Law: z A new generation of memory chips is introduced every 3 years z Each new generation has 4 times as much memory as its predecessor y Computer technology doubles every 1. 5 years: Example: DRAM capacity 100, 000 64 M K b it c a p a cit y 16 M 10, 000 4 M 1 M 1000 256 K 100 64 K 16 K 10 1976 1978 1980 1982 1984 1986 1988 Year o f introduction 1990 1992 1994 1996 18

Technology => dramatic change z. Processor ylogic capacity: about 30% per year yclock rate: about 20% per year z. Memory y. DRAM capacity: about 60% per year (4 x every 3 years) y. Memory speed: about 10% per year y. Cost per bit: improves about 25% per year z. Disk ycapacity: about 60% per year Question: Does every thing look OK? 20

Software Evolution. z z Machine language Assembly language High-level languages Subroutine libraries z There is a large gap between what is convenient for computers & what is convenient for humans z Translation/Interpretation is needed between both 21

Language Evolution swap (int v[], int k) { int temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; } swap: muli $2, $5, 4 add $2, $4, $2 lw $15, 0($2) lw $18, 4($2) sw $18, 0($2) sw $15, 4($2) jr $31 0 00 0 0 1 0 00 00 1 1 0 0 00 0 0 1 1 1 0 0 0 0 0 1 00 0 0 1 1 0 0 0 0 00 00 0 1 1 1 1 0 0 0 00 00 1 0 1 0 1 1 0 0 1 0 0 0 0 00 00 0 1 0 1 1 0 0 0 0 00 00 1 0 00 0 1 1 1 0 0 0 0 00 0 0 0 1 0 0 0 High-level language program (in C) Assembly language program (for MIPS) Binary machine language program (for MIPS) 22

HW - SW Components z Hardware y Memory components x Register file x memory x Disks y Functional components x Adder, multiplier, dividers, . . . x Comparators x Control signals z Software y Data x Simple • Characters • Integers • Floating-point • Pointers x Structured • Arrays • Structures ( records) y Instructions x Data transfer x Arithmetic x Shift x Control flow x Comparison x. . . 23

Things You Will Learn z Assembly language introduction/Review z How to analyze program performance z How to design processor components z How to enhance processors performance (caches, pipelines, parallel processors, multiprocessors) 24

The Processor Chip 25

Processor Chip Major Blocks • Example: Intel Pentium • Area: 91 mm 2 • ~ 3. 3 million transistors ( 1 million for cache memory) Control Data cache Instruction cache Bus Integer datapath Branch Floatingpoint datapath 26

Memory z Categories y Volatile memory x Loses information when power is switched-off y Non-volatile memory x Keeps information when power is switched-off z Types y Cache: x Volatile x Fast but expensive x Smaller capacity x Placed closer to the processor y Main memory x Volatile x Less expensive x More capacity y Secondary memory x Nonvolatile x Low cost x Very slow x Unlimited capacity 27

Input-Output (I/O) z I/O devices have the hardest organization y Wide range of speeds x. Graphics vs. keyboard y Wide range of requirements x. Speed x. Standard x. Cost. . . y Least amount of research done in this area 28

Our Primary Focus z The processor (datapath and control) y Implemented using millions of transistors y Impossible to understand by looking at each transistor y We need abstraction x. Hides lower-level details to offer simple model at higher level x. Advantages • Intensive & thorough research into the depths • Reveals more information • Omits unneeded details • Helps us cope with complexity x. Examples of abstraction: • Language hierarchy • Instruction set architecture (ISA) 29

Instruction Set Architecture (ISA) z Instruction set: y Complete set of instructions used by a machine z ISA: y Abstract interface between the HW and lowest-level SW. It encompasses information needed to write machine-language programs including x. Instructions x. Memory size x. Registers used x. . . 30

Instruction Set Architecture (ISA) z ISA is considered part of the SW z Several implementations for the same ISA can exist z Modern ISA’s: y 80 x 86/Pentium/K 6, Power. PC, DEC Alpha, MIPS, SPARC, HP y We are going to study MIPS z Advantages: y Different implementations of the same architecture y Easier to change than HW y Standardizes instructions, machine language bit patterns, etc. z Disadvantage: y Sometimes prevents using new innovations 31

Instruction Set Architecture (ISA) • Instruction Execution Cycle Fetch Instruction From Memory Decode Instruction determine its size & action Fetch Operand data Execute instruction & compute results or status Store Result in memory Determine Next Instruction’s address 32

What Should we Learn? z A specific ISA (MIPS) z Performance issues - vocabulary and motivation z Instruction-Level Parallelism z How to Use Pipelining to improve performance z Exploiting Instruction-Level Parallelism w/ Software Approach z Memory: caches and virtual memory z I/O 33

What is Expected From You? • • Read textbook & readings! Be up-to-date! Come back with your input & questions for discussion! Appreciate and participate in teamwork! 34