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C. A. D. Intellectual Agenda u Roadmapping: “Living Roadmap” to connect applications, architectures, components, C. A. D. Intellectual Agenda u Roadmapping: “Living Roadmap” to connect applications, architectures, components, technologies s Design envelopes; Impacts of innovations; FCRP portfolio gaps s Synergies: Drivers, Power-Energy, Reliability, C 2 S 2 Fabrics, MSD, IFC u Focus on Si. P physical implementation platforms (CLC, SOS) s Huge hole in FCRP understanding s Need technology and cost modeling, tools, implementation, roadmapping s Concrete high-end design driver (initially, CLC Si. P driver highlighting logic-DRAM integration, DARPA MSP (Boeing STAP)) u Interfaces and standards (“infrastructure”) for design process Internal to flows and methodologies 030320 s abk 1

Concrete Outcomes u Task 1: Living Roadmap (from applications through ITRS technologies) s s Concrete Outcomes u Task 1: Living Roadmap (from applications through ITRS technologies) s s Cost-aware Gaps research + tool needs t s Manufacturing handoff, die-package interface, variability, global signaling, synchronization, power delivery, robustness, … GTX grows into a system-level analysis tool that is validated with design drivers u Task 2 A: Develop Si. P implementation platforms s Platform-specific tools and roadmapping u Task 2 B: High-End (“Radar on a Chip”) Driver s Demonstration vehicle for overall GSRC methodology and CLC Si. Pspecific tools s Driver scaling + extrapolation s Integration paths for GSRC’s and other design methodologies u Task 3: Design process infrastructure s Design data models and interfaces current enablers, future standards s Reusable, composable solvers rapid flow synthesis/optimization 030320 abk 2

Working Sessions u Goals s Drivers: Which ones? How they unify GSRC activities? Key Working Sessions u Goals s Drivers: Which ones? How they unify GSRC activities? Key research gaps? Roadmaps of functional requirements, technology showstoppers s Roadmapping: PED and Reliability s Design Infrastructure: Open. Access data model and extensions; mini-flows and benchmarking (placement focus) u Today 10: 30 – noon (joint with PED and Reliability) s CLC SIP and MSP, Radar-on-Chip Driver (Dai) s Pico. Radio (Pico. Node) Driver (Rabaey) u Today 1: 00 – 2: 30 pm s Home Gateway Driver (Kulkarni, Keutzer, Hwu) – brainstorming session u Today 3: 00 – 4: 00 pm s Roles of Drivers in new GSRC 030320 abk 3

Driver Discussions u Which ones? u How do they unify GSRC activities? u Key Driver Discussions u Which ones? u How do they unify GSRC activities? u Key research gaps? u Roadmaps of functional requirements, technology showstoppers u Today 10: 30 – noon (joint with PED and Reliability) s s s CLC SIP and MSP, Radar-on-Chip Driver (Dai) Pico. Radio (Pico. Node) Driver (Rabaey) Micro. Lab (alternative space) (Gupta) u Today 1: 00 – 2: 30 pm s Home Gateway Driver (Kulkarni, Keutzer, Hwu) – brainstorming session u Today 3: 00 – 4: 00 pm s Roles of Drivers in new GSRC 030320 abk 4

Driver Discussions u A DRIVER IS: s A concrete design for a specific application Driver Discussions u A DRIVER IS: s A concrete design for a specific application s (Lots of $, very few papers ) u WHAT (D&T) PROBLEM IS THE DRIVER TRYING TO GET US TO SOLVE? s s s s Continuation of the Moore’s Law for COST Scalability of design or its infrastructure Conceptualization (modeling, representation, validation) of systems Unreliability and Unpredictability at component level (Validation should be on this list, but how exactly are the drivers such as Radar-On-Chip driving validation? ) (Should Power be a first-class citizen? ) (N. B. : “Mixed-*” is mostly implicit in Conceptualization) u WHAT ARE DELIVERABLES ASSOCIATED WITH A DRIVER? s s Design data (spec, arch, netlist, implementation, simulation, verification) and hardware Tools 030320 abk 5

Driver Discussions u Axes for Drivers: s Metrics: heterogeneity, performance, power, size, reliability/RAS, cost Driver Discussions u Axes for Drivers: s Metrics: heterogeneity, performance, power, size, reliability/RAS, cost s Impact: intrinsic value, interest (DARPA? HP/IBM/? Or Bechtel/PGE/? ), technology leading edge s Synergy: semiconductor technologies, bridges within GSRC, package, system u System-Level vs. Fabric/Block Level s Application-level vs. implementation-level challenges s Bottom-up super-components (= top-down subsystems) that enable system: are these created by GSRC or C 2 S 2? u Candidates s Batteryless t t s Ambient embedded networked sensing (= proxy for “next-gen”) Pico. Node, Lab. On. Chip, MICA, Smart. Dust High-performance computing t t t 030320 abk SIP / stacking: Radar On Chip: STAP DSP + Memory integration, CLCSIP physical platform General-purpose computing (500 5 GHz MIPS cores on chip) Utility computing (data center 6

Driver Discussions u Drivers + Infrastructure = third dimension s Are we picking drivers Driver Discussions u Drivers + Infrastructure = third dimension s Are we picking drivers as a minimum-size cover, or are we picking drivers as “impactful”? Need to bound the goals, scope, … of this discussion s Communication-based, soft systems s DFX: Test, Verification, Power, Reliability, … u Other s Logistics t t s s Leveraging (“how we do it now”), not building (rather, “hypothesis testing”) Common access Need a driver taxonomy + metrics: access/interfacing, heterogeneity, etc. Links: Open. GIS. org, Security (SEC Disaster Recovery + Business Continuance), Recover-Oriented Computing, … Home Gateway: How does drive VLSI and IC design? What criticality is being overcome by spending $$$ on this driver? 030320 abk 7

PD Open Problems (Payman and Amir) u Incremental u Combined Placement and Floorplanning s PD Open Problems (Payman and Amir) u Incremental u Combined Placement and Floorplanning s locks solution into a bad subspace s Timing is a constraint (not an objective); WL is an objective s Problem = lack of understanding of interrelationships between different objectives, e. g. , timing, area (fixed-die) and congestion t s N. B. : WL may not really be an objective: it is a proxy for congestion (area) Issue of capturing timing in top-down partitioning-based placement (partitioning is net-based; timing is path-based) u How is SI solved at placement? u IR drop placement? IR drop has impact on timing and reliability and hence important u Variability-aware placement? 030320 abk 8

PD Open Problems (Payman and Amir) u Thermal placement (not just dynamic power minimization) PD Open Problems (Payman and Amir) u Thermal placement (not just dynamic power minimization) s Given activities of all gates, find a placement to minimize a linear combination of dynamic power and maximum thermal variation u Hierarchy? s Probably moving to u Datapath-based (timing-constrained) placement s People have tried but have not achieved notably better results s 2 literature from late 1980’s: Ebeling et al. subgraph isomorphism, Odawara/Szymanski/Nijssen-Jess/Varadarajan-Arikati on regularity extraction 030320 abk 9

PD Open Problems (Payman and Amir) u Power implications (voltage islands) s Chuck also PD Open Problems (Payman and Amir) u Power implications (voltage islands) s Chuck also mentions this s Clock gating s Multi-Vdd islands: granularity of several hundred cells (? ) – 1 -2 rows min in V, stripe pitch min in H s Ground islands (shutdown of blocks keeping memory partially powered up) s Cf. Amir’s work at Northwestern ~1995 u Placement for BIST (check with Tim Cheng et al. ) u Signal Integrity Issues (crosstalk handling at floorplan and placement) u Clock distribution u Suggestion: Single-width, single-pitch cell layout, synthesis, place and route flow: WOULD BE HEROES !!! (Phase. Phirst!, SCAAM, etc. == next -generation lithography proposals, all of which depend on “hyperresolution” (“ 2 -beam imaging”) basically, only one direction and one pitch will print (the layout is a subset of a grating). Goal: C. A. D. people should prove a one-time, bounded hit on Moore’s Law (e. g. , 30% density) but then scalability of SP&R thereafter. u X, Y Architectures March 5 th EE Design ? u Design for Variability u Backend Process Optimization s s Complex objective: marketing, methodology, integration Marketing: BEOL should be optimized for many designs (derivatives, etc. ) – 10 030320 abk

Working Sessions u Friday parallel session #1: Roadmapping s 9: 00 – 11: 00 Working Sessions u Friday parallel session #1: Roadmapping s 9: 00 – 11: 00 am (joint with PED and Reliability) s Background (Energy, Reliability, Variability) s Panel: PED Roadmapping Needs and Research Gaps s 11: 00 am – noon s Roadmapping of Process Variability, Cost Optimizations u Friday parallel session #2: Infrastructure, Benchmarking s 9: 00 – 10: 00 am s BX and Benchmarking Status s 10: 00 am – 11: 00 am s Placement-Centered Directions (Mini-Flows, New Problems) s 11: 00 am – noon s Concrete steps with Open. Access u Friday 1: 30 – 2: 30 pm s Discussion of C. A. D. Roles in the “New GSRC”: collaborations, projects, milestones 030320 abk 11