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Appendix A—Digital Logic A-1 Some Definitions Combinational logic: a digital logic circuit in which Appendix A—Digital Logic A-1 Some Definitions Combinational logic: a digital logic circuit in which logical decisions are made based only on combinations of the inputs (e. g. , an adder). Sequential logic: a circuit in which decisions are made based on combinations of the current inputs as well as the past history of inputs (e. g. , a memory unit). Finite state machine: a circuit which has an internal state, and whose outputs are functions of both current inputs and its internal state (e. g. , a vending machine controller). Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-2 The Combinational Logic Unit Translates a set of inputs into Appendix A—Digital Logic A-2 The Combinational Logic Unit Translates a set of inputs into a set of outputs according to one or more mapping functions. Inputs and outputs for a CLU normally have two distinct (binary) values: high and low, 1 and 0, 0 and 1, or 5 v and 0 v, for example. The outputs of a CLU are strictly functions of the inputs, and the outputs are updated immediately after the inputs change. A set of inputs i 0–in are presented to the CLU, which produces a set of outputs according to mapping functions f 0–fm. i 0 in Combinational logic unit Computer Systems Design and Architecture by V. Heuring and H. Jordan f 1 . . . i 1 . . . Fig A. 1 f 0 fm © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-3 Truth Tables Developed in 1854 by George Boole Further developed Appendix A—Digital Logic A-3 Truth Tables Developed in 1854 by George Boole Further developed by Claude Shannon (Bell Labs) Outputs are computed for all possible input combinations (how many input combinations are there? Consider a room with two light switches. How must they work †? Fig. A. 2 Inputs Output Light Z “Hot” A 0 1 1 1 Switch B 0 0 Switch A Z 0 GND B 0 1 1 1 0 †Don't show this to your electrician, or wire your house this way. This circuit definitely violates the electric code. The practical circuit never leaves the lines to the light "hot" when the light is turned off. Can you figure how? Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-4 Fig A. 4 Truth Tables Showing All Possible Functions of Appendix A—Digital Logic A-4 Fig A. 4 Truth Tables Showing All Possible Functions of Two Binary Variables The more frequently used functions have names: AND, XOR, NOR, XOR, and NAND. (Always use upper-case spelling. ) Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-5 Logic Gates and Their Symbols A B Fig. A. 5 Appendix A—Digital Logic A-5 Logic Gates and Their Symbols A B Fig. A. 5 Logic Gate Symbols for AND, OR, Buffer, and NOT Boolean functions F A B F 0 0 1 1 0 1 1 1 0 1 A B F = AB 0 1 A B F=A+B AND OR A F 0 1 0 1 1 0 A F=A Buffer A F=A NOT (Inverter) Note the use of the “inversion bubble. ” Be careful about the “nose” of the gate when drawing AND vs. OR. Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-6 Fig A. 6 Logic Gate Symbols for NAND, NOR, XOR, Appendix A—Digital Logic A-6 Fig A. 6 Logic Gate Symbols for NAND, NOR, XOR, and XNOR Boolean functions A B F 0 0 1 1 1 0 0 1 0 1 A B F=AB 0 1 A B F=A+B NAND NOR A B F 0 0 1 1 A B F 0 1 1 0 0 0 1 1 1 0 0 1 0 1 F=A+B Exclusive-OR (XOR) Computer Systems Design and Architecture by V. Heuring and H. Jordan A B 0 1 F=A B Exclusive-NOR (XNOR) © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-7 Fig A. 7 Variations of Basic Logic Gate Symbols (a) Appendix A—Digital Logic A-7 Fig A. 7 Variations of Basic Logic Gate Symbols (a) 3 inputs (b) A negated input Computer Systems Design and Architecture by V. Heuring and H. Jordan (c) Complementary outputs © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-8 Fig A. 9 Assignments of Logical 0 and Logical 1 Appendix A—Digital Logic A-8 Fig A. 9 Assignments of Logical 0 and Logical 1 to Voltage Ranges +5 V Logical 1 2. 4 V Logical 1 2. 0 V Forbidden range 0. 4 V 0 V Forbidden range 0. 8 V Logical 0 (a) At the output of a logic gate Computer Systems Design and Architecture by V. Heuring and H. Jordan Logical 0 0 V (b) At the input to a logic gate © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-9 Tbl A. 1 The Basic Properties of Boolean Algebra Principle Appendix A—Digital Logic A-9 Tbl A. 1 The Basic Properties of Boolean Algebra Principle of duality: The dual of a Boolean function is gotten by replacing AND with OR and OR with AND, constant 1 s by 0 s, and 0 s by 1 s Postulates Theorems Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-10 De. Morgan’s Theorem A B 0 0 1 1 1 Appendix A—Digital Logic A-10 De. Morgan’s Theorem A B 0 0 1 1 1 0 0 1 Fig A. 11 AB = A+B = A B 1 0 0 De. Morgan’s theorem: A + B = A B Fig A. 12 A B F=A+B A B F=AB Discuss: Applying De. Morgan’s theorem by “pushing the bubbles” and “bubble tricks. ” Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-11 Fig A. 16 Four Notations Used at Circuit Intersections Computer Appendix A—Digital Logic A-11 Fig A. 16 Four Notations Used at Circuit Intersections Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-12 Positive versus Negative Logic • Positive logic: truth, or assertion Appendix A—Digital Logic A-12 Positive versus Negative Logic • Positive logic: truth, or assertion is represented by logic 1, higher voltage; falsity, de- or unassertion, logic 0, is represented by lower voltage. • Negative logic: truth, or assertion is represented by logic 0 , lower voltage; falsity, de- or unassertion, logic 1, is represented by lower voltage Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-13 Digital Components High-level digital circuit designs are normally made using Appendix A—Digital Logic A-13 Digital Components High-level digital circuit designs are normally made using collections of logic gates referred to as components, rather than using individual logic gates. The majority function can be viewed as a component. Levels of integration (numbers of gates) in an integrated circuit (IC): • • Small-scale integration (SSI): 10– 100 gates. Medium-scale integration (MSI): 100– 1000 gates. Large-scale integration (LSI): 1000– 10, 000 logic gates. Very large scale integration (VLSI): 10, 000–upward. These levels are approximate, but the distinctions are useful in comparing the relative complexity of circuits. Let us consider several useful MSI components. Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-14 SN 7400 QUADRUPLE 2 -INPUT POSITIVE-NAND GATES description These devices Appendix A—Digital Logic A-14 SN 7400 QUADRUPLE 2 -INPUT POSITIVE-NAND GATES description These devices contain four independent 2 -input NAND gates. function table (each gate) INPUTS A B Fig A. 20 Simplified Data Sheet H L X package (top view) OUTPUT Y H X L schematic (each gate) 1 A 1 B 1 Y 2 A 2 B 2 Y GND L H H 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4 B 4 A 4 Y 3 B 3 A 3 Y 4 k VCC 130 1. 6 k A B Y absolute maximum ratings Supply voltage, VCC Input voltage: Operating free-air temperature range: Storage temperature range 7 V 5. 5 V 0°C to 70°C – 65°C to 150°C 1 k GND recommended operating conditions MIN NOM MAX logic diagram (positive logic) VCC VIH 4 Y Y=AB High-level output current IOL 3 Y Low-level input voltage IOH 2 Y High-level input voltage VIL 1 Y Supply voltage Low-level output current TA 1 A 1 B 2 A 2 B 3 A 3 B 4 A 4 B 4. 75 Operating free-air temperature UNIT 5 5. 25 V 2 V 0. 8 V – 0. 4 m. A 16 m. A 70 °C 0 electrical characteristics over recommended operating free-air temperature range VALUE OPERATING CONDITIONS VOH VCC = MIN, VIL = 0. 8 V, IOH = – 0. 4 m. A VOL TYP 3. 4 VCC = MIN, VIH = 2 V, IOL = 16 m. A IIH MIN 2. 4 MAX UNIT V 0. 4 V VCC = MAX, VI = 2. 4 V 40 A IIL VCC = MAX, VI = 0. 4 V – 1. 6 m. A ICCH VCC = MAX, VI = 0 V 4 8 m. A ICCL VCC = MAX, VI = 4. 5 V 12 22 m. A 0. 2 switching characteristics, VCC = 5 V, TA = 25° C PARAMETER t. PLH t. PHL FROM (input) A or B Computer Systems Design and Architecture by V. Heuring and H. Jordan TO (output) TEST CONDITIONS MIN NOM MAX UNIT Y RL = 400 CL = 15 p. F 11 22 ns 7 15 ns © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-15 The Multiplexer Data inputs Fig A. 21 Block Diagram and Appendix A—Digital Logic A-15 The Multiplexer Data inputs Fig A. 21 Block Diagram and Truth Table D 0 00 D 1 01 D 2 10 D 3 11 A F B F 0 0 1 1 0 1 D 0 D 1 D 2 D 3 A B Control inputs F = A B D 0 + A B D 1 + A B D 2 + A B D 3 Fig A. 22 AND-OR Circuit Implementation Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-16 The Demultiplexer (DEMUX) Fig A. 25 Block Diagram and Truth Appendix A—Digital Logic A-16 The Demultiplexer (DEMUX) Fig A. 25 Block Diagram and Truth Table 00 F 0 01 F 1 10 F 2 11 F 3 F 2 = D A B F 1 = D A B 0 0 0 0 0 1 1 0 0 0 1 F 0 = D A B F 0 F 1 F 2 F 3 1 A B 0 D D 0 1 0 0 1 1 0 0 0 1 F 3 = D A B Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

A-17 Appendix A—Digital Logic Fig A. 32 A Programmable Logic Array A PLA is A-17 Appendix A—Digital Logic Fig A. 32 A Programmable Logic Array A PLA is a customizable AND matrix followed by a customizable OR matrix Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

A-18 Appendix A—Digital Logic Fig A. 33 Simplified Representation of a PLA Computer Systems A-18 Appendix A—Digital Logic Fig A. 33 Simplified Representation of a PLA Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-19 Speed and Performance The speed of a digital system is Appendix A—Digital Logic A-19 Speed and Performance The speed of a digital system is governed by • the propagation delay through the logic gates and • the propagation across interconnections. Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-20 Fig A. 47 Propagation Delay for a NOT Gate (Adapted Appendix A—Digital Logic A-20 Fig A. 47 Propagation Delay for a NOT Gate (Adapted from Hamacher et al. , 1990) Transition time +5 V 10% The NOT gate input changes from 1 to 0 (Fall time) 50% (2. 5 V) 0 V 90% Propagation delay (Latency) Transition time +5 V (Rise time) The NOT gate output changes from 0 to 1 0 V 10% 90% 50% (2. 5 V) Time Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-21 Fan-in May Affect Circuit Depth Fig A. 49 A Logic Appendix A—Digital Logic A-21 Fan-in May Affect Circuit Depth Fig A. 49 A Logic Gate Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-22 Sequential Logic The combinational logic circuits we have been studying Appendix A—Digital Logic A-22 Sequential Logic The combinational logic circuits we have been studying so far have no memory. The outputs always follow the inputs. There is a need for circuits with a memory, which behave differently depending upon their previous state. An example is the vending machine, which must remember how many and what kinds of coins have been inserted, and which behave according to not only the current coin inserted, but also upon how many and what kind of coins have been deposited previously. These are referred to as finite state machines, because they can have at most a finite number of states. Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-23 . . . ik Combinational logic unit . . . Appendix A—Digital Logic A-23 . . . ik Combinational logic unit . . . Inputs fo Outputs fm . . . io . . . Fig A. 50 Classical Model of a Finite State Machine State bits Q 0 D 0 . . . s 0 Qn D n sn Synchronization signal Delay elements (one per state bit) Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-24 A. 51 A NOR Gate with a Lumped Delay A Appendix A—Digital Logic A-24 A. 51 A NOR Gate with a Lumped Delay A A B A+B 1 0 1 0 Timing behavior This delay between input and output is at the basis of the functioning of an important memory element, the flip-flop. Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-25 A. 52 An S-R Flip-Flop Qt R Q Q Rt Appendix A—Digital Logic A-25 A. 52 An S-R Flip-Flop Qt R Q Q Rt Qi+1 S 0 0 0 1 0 0 R 0 0 1 1 (disallowed) Q 1 1 1 0 0 1 0 1 Q 1 S St 1 1 (disallowed) 2 2 Timing behavior The S-R flip-flop is an active-high (positive logic) device. Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-26 Fig A. 53 Converting a NOR S-R to an NAND Appendix A—Digital Logic A-26 Fig A. 53 Converting a NOR S-R to an NAND S-R Active-high NOR Implementation Push bubbles (De. Morgan’s) Computer Systems Design and Architecture by V. Heuring and H. Jordan Rearrange bubbles Convert from bubbles to active-low signal names © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-27 Fig A. 55 A Clock Waveform In a positive logic Appendix A—Digital Logic A-27 Fig A. 55 A Clock Waveform In a positive logic system, the “action” happens when the clock is high, or positive. The low part of the clock cycle allows propagation between subcircuits, so their inputs are stable at the correct value when the clock next goes high. Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-28 A. 56 A Clocked S-R Flip-Flop S R S Q Appendix A—Digital Logic A-28 A. 56 A Clocked S-R Flip-Flop S R S Q CLK Q Q R Q 2 3 Timing behavior The clock signal, CLK, turns on the inputs to the flip-flop. Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-29 Fig A. 57 A Clocked D (Data) Flip-Flop Circuit D Appendix A—Digital Logic A-29 Fig A. 57 A Clocked D (Data) Flip-Flop Circuit D D Q CLK Q Q Q D Q 2 Symbol C Q 2 Timing behavior The clocked D flip-flop, sometimes called a latch, has a potential problem: If D changes while the clock is high, the output will also change. The Master. Slave flip-flop solves this problem. Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-30 A. 58 A Master-Slave Flip-Flop Circuit D Master D CLK Appendix A—Digital Logic A-30 A. 58 A Master-Slave Flip-Flop Circuit D Master D CLK Slave D QM D QS CLK C C QS QM QS D Q QS Symbol Q 3 2 2 2 Timing behavior The rising edge of the clocks new data into the master, while the slave holds previous data. The falling edge clocks the new master data into the slave. Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-31 Fig A. 59 The Basic J-K Flip-Flop • The J-L Appendix A—Digital Logic A-31 Fig A. 59 The Basic J-K Flip-Flop • The J-L flip-flop eliminates the S = R = 1 problem of the S-R flip-flop, because Q enables J while Q' disables K, and vice versa. • However there is still a problem. If J goes momentarily to 1 and then back to 0 while the flip-flop is active and in the reset, the flip-flop will “catch” the 1. • This is referred to as “ 1’s catching. ” • The J-K master-slave flip-flop solves this problem. Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

A-32 Appendix A—Digital Logic Fig A. 61 A Master-Slave J-K Flip-Flop Computer Systems Design A-32 Appendix A—Digital Logic Fig A. 61 A Master-Slave J-K Flip-Flop Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-33 Fig A. 62 Negative Edge-Triggered D Flip-Flop Amplitude Stores D Appendix A—Digital Logic A-33 Fig A. 62 Negative Edge-Triggered D Flip-Flop Amplitude Stores D R Q CLK Time Q S Cycle time = 25 ns Main latch D Stores D When the clock is high, the two input latches output 0, so the main latch remains in its previous state regardless of changes in D. When the clock goes high-low, values in the two input latches will affect the state of the main latch. While the clock is low, D cannot affect the main latch. Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-34 Finite State Machine Design Counter has a clock input, CLK, Appendix A—Digital Logic A-34 Finite State Machine Design Counter has a clock input, CLK, and a RESET input. Has two output lines, which must take values of 00, 01, 10, and 11 on subsequent clock cycles. Fig A. 63 A Modulo-4 Counter Time (t) 4 3 2 1 0 Time (t) q 0 01100 q 1 3 -bit synchronous s 0 counter 00001 01010 RESET It requires two flip-flops to store the state. Computer Systems Design and Architecture by V. Heuring and H. Jordan s 1 D D Q s 1 CLK Q s 0 Q Q © 1997 V. Heuring and H. Jordan

Appendix A—Digital Logic A-35 Mealy versus Moore Machines Mealy model: Outputs are functions of Appendix A—Digital Logic A-35 Mealy versus Moore Machines Mealy model: Outputs are functions of inputs and present state. Previous FSM designs were Mealy machines, because next state was computed from present state and inputs. x 1 x 0 5 x 5 PLA z 2 z 1 z 0 Moore model: Outputs are functions of present state only. 0 x 1 00 01 4 -to-1 10 MUX 11 D Q s 0 z 0 Q D Q s 1 z 1 Q Q D s 0 CLK Q D s 1 Computer Systems Design and Architecture by V. Heuring and H. Jordan CLK Both are equally powerful. © 1997 V. Heuring and H. Jordan

A-36 Appendix A—Digital Logic Fig A. 78 A 4 -Bit Register Gate-Level View Fig A-36 Appendix A—Digital Logic Fig A. 78 A 4 -Bit Register Gate-Level View Fig A. 79 Abstract Representation of a 4 -Bit Register Chip-Level View Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

A-37 Appendix A—Digital Logic Fig A. 80 Internal Layout and Block Diagram for Left-Right A-37 Appendix A—Digital Logic Fig A. 80 Internal Layout and Block Diagram for Left-Right Shift with Parallel Read/Write Capabilities c 1 c 0 D 2 D 3 D 1 D 0 Left shift out Left shift in Right shift in D Q c 0 c 1 D Q D Q Right shift out CLK Enable (EN) Q 3 Control Q 2 Q 1 Q 0 Function c 1 c 0 0 0 No change 0 1 Shift left 1 0 Shift right 1 1 Parallel load Left shift in Left shift out D 3 D 2 D 1 D 0 c 1 Q 3 Q 2 Q 1 Q 0 Computer Systems Design and Architecture by V. Heuring and H. Jordan Right shift out Right shift in © 1997 V. Heuring and H. Jordan

A-38 Appendix A—Digital Logic Fig A. 81 A Modulo(8) Ripple Counter Note the use A-38 Appendix A—Digital Logic Fig A. 81 A Modulo(8) Ripple Counter Note the use of the T flip-flops. They are used to toggle the input of the next flipflop when its output is 1. Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan