An Introduction to BORPH Hayden Kwok-Hay So University

An Introduction to BORPH Hayden Kwok-Hay So University of Hong Kong Aug 2, 2008 CASPER Workshop II

Reconfigurable Computing for Everyone • Language • Design Environment • Applications • OS • System Integration Hardware • System Integration Software • Language • Design Environment • Applications • OS BORPH

BORPH n n Berkeley Operating system for Re. Programmable Hardware OS for reconfigurable computers l n Treats reconfigurable hardware as computational resources UNIX interface to HW designs Familiar to both software and hardware engineers l Design language independent l n Goal: Make FPGA-based reconfigurable computers easy to use

Conventional View of FPGA Systems User Process (SW) Software pipe User Process (SW) User Library file User Process (SW) socket IPC OS Kernel Hardware Device Driver Hardware Platform (Network, UART, HD…) FPGA “coprocessor” Master-Slave Relationship

BORPH Layers User Process (SW) Peer-to-Peer Relationship User Process (SW) Software User Library file pipe IPC BORPH Kernel Hardware Device Driver Hardware Platform (Network, UART, HD…) socket ioreg virtual file Hardware User Library User Process (HW)

Overview of BORPH Concepts n ioreg virtual file interface l Hardware file I/O SW Software n Hardware process Hardware syscall interface Interacting with an FPGA l Hardware n SW file pipe SW User Library IPC BORPH Kernel Device Driver socket ioreg Hardware User Library Hardware Platform (Network, UART, HD…) HW HW

Hardware Process An executing instance of a hardware design n Normal UNIX process l n n Has pid, check status with ps, kill, etc Unit of management Created when a BORPH Object File (BOF) file is exec-ed l SW SW: An executing instance of a program Kernel selects and configure hardware region automatically Software l Hardware n SW file pipe SW User Library IPC BORPH Kernel Device Driver socket ioreg Hardware User Library Hardware Platform (Network, UART, HD…) HW HW

HW Processes I/O Standard UNIX I/O mechanism l l n Similar to SW Hide details from users l n SW I/O managed by kernel Software n SW File I/O, pipe, signal e. g. HW-SW, HW-HW UNIX file pipe HW specific service l Hardware n file pipe SW User Library IPC BORPH Kernel Device Driver socket ioreg Hardware User Library Hardware Platform (Network, UART, HD…) HW ioreg virtual file system Don’t ask “How do I … in HW”. Think: “What if it were SW? ” HW

ioreg Virtual File System n Maps user defined hardware constructs as virtual files under the process’s /proc/<pid>/hw/ioreg/ directory l l l n Example: l n n Single word register Memory: On-chip + Off-chip FIFO /proc/123/hw/ioreg/COUNTERVAL ioreg information embedded in the executing BOF file read and write system calls translated to message packet by the kernel l Any UNIX program can communicate with hardware processes n n n Shell: echo 1 > /proc/123/hw/ioreg/enable C: MEM_FILE = fopen(“/proc/123/hw/ioreg/My. Memory”, “r”); fread(swbuf, 1, MEM_SIZE, MEM_FILE); Python, Java, etc…

Example BORPH counter. bof Kernel Message Parsing 0 1 HWR en val Configured cntval counter cnten bash$. /counter. bof & [1] 2458 bash$ ps PID TTY TIME CMD 2456 pts/4 00: 00 bash 2458 pts/4 00: 00 counter. bof 2507 pts/4 00: 00 ps bash$ cat /proc/2458/hw/ioreg/cntval A 3 B 498 E 0 bash$ cat /proc/2458/hw/ioreg/cntval B 289 E 906 bash$ echo 0 > /proc/2458/hw/ioreg/cnten bash$ cat /proc/2458/hw/ioreg/cntval C 102 F 34 D bash$ kill -9 2458 [1]+ Killed counter. bof bash$

Hardware File I/O n n Access to the general file system from hardware processes Debug by printing l n printf Read test vectors, record output Analog Frontend A/D Baseband Process Upper Layer bash$ receiver. bof < file. in > file. out n SW/HW processes chained by file pipe Decode video. in Resize Edge Detect Encode video. out bash$ decode video. in | resize | edgdet. bof | encode > video. out

Simulink-Based Design Flow n Simulink: A block based design environment on top of Matlab l n n Cycle-accurate, bitaccurate simulation in Simulink Single-button to implementation l n Familiar to communication/ protocol designers Based on Xilinx System Generator In-house library for BEE 2 specific blocks l l I/O BORPH integration

From Simulink to BOF System Insertion Block Instantiation Synthesis, Map, Place & Route Config Generation counter. bof

Current Implementation on BEE 2 n n n BORPH on Power. PC of center control FPGA 1 user FPGA programmed for each hardware process Based on Linux 2. 4. 30 kernel User Design Software reuse l Debian root filesystem l User Design BORPH User Design Select. Map MGT Direct Conn Ethernet

Memory Controller DMA Cntrl Select. Map Control On-Chip Memory PPC ioreg PLB-OPB Bridge PPC User FPGA Ethernet Controller PLB-OPB Bridge Control FPGA System Architecture on BEE 2 ioreg Shared BRAM Select. Map FIFO Shared FIFO A iock n bfsio Bus mastering DMA controller on Control FPGA l n User Design Improve configuration and data transfer Direct HW access to Select. Map FIFO on User FPGA l Improved File I/O speed

On to ROACH… n n n 1 AMCC Power. PC 440 EPx 1 Xilinx V 5 FPGA BORPH runs on PPC l n v 2. 0 1 hardware process at a time User Design BORPH MGT Direct Conn Gb Ethernet

BORPH v 2. 0 n Based on Linux 2. 6. 25 kernel l Future n proof Modular l Easy to port to different platforms l e. g. Implementing ioreg interface for a new platform requires only 6 functions. n Many ports planned: l Backport to BEE 2 l PC Desktop with FPGA card

Summary n BORPH is here, ready to use l Free, open source l If you know Linux, you can use it n BORPH is extensible l Able n to run on anything that runs Linux BORPH is more than a way to do I/O l Covers all aspect of reconfigurable computing