An Engineering Manager s View of Verification Vendors Joseph

An Engineering Manager’s View of Verification Vendors Joseph Hupcey III January 3, 2003 January 2003 1

Overview • Scope, Point of View, and Methodology • Direct Competitors: Functional & Assertion-Based Verification Vendors • Formal Verification Vendors • Other Players • Observations • Conclusions January 2003 2

Scope, POV, and Methodology • Scope – Review of the functional and formal verification tool space • Point Of View – A verification engineering manager ã Experienced in manual Verilog and VHDL test methodologies. ã Open to spend time and some $ on evaluating new verification tools ã Has existing IP in Verilog, VHDL, C; but will sacrifice for demonstrated ROI • Methodology – Vendor WWW Sites – Industry Sites: Verification Guild Archive, Deep. Chip. com, Accellera. org – Trade Publications: EET, EDTN, EDA Tools Cafe – Financial Analyst Reports – Minimal pricing data available January 2003 3

Direct Competitor: Products • Smart Verification with VCS 7 • VERA Test Bench automation • Open. Vera Assertions (OVA), • OV Verification IP Pitch “Synopsys’ Functional Verification tools are a (friendly and manageable) extension of new VCS 7. 0” January 2003 4

Direct Competitor: (continued) Reactions Pro • • • OPEN Vera - “open” keyword a positive, and a web site (www. openvera. com) to back it up Assertion Based Ver. + OVA white papers informative --> enough VERA language shown to inspire interest, confidence Comforting subtext: Integration (VCS at center of the block diag, etc. ) Con • • Test and code coverage analysis tools not really shown ROI case not strongly made Low number / medium strength testimonials Co-Design+Superlog: Other than engineering team, impact of 4/02 acquisition is not clear (Verification constructs into next gen. Verilog? ) (Intel is quoted!) January 2003 5

Direct Competitor: Products • Verification Cockpit • Test Builder • Transaction Explorer • Cadence ABV (Sugar) • NC - Cov • Transaction Verification Modules (TVM) • Verification Reuse Methodology (VRM) Pitch “VC + TB tools support fast, resource efficient C++ Transactions. Methodology leverages your existing C/C++ programming expertise. ” January 2003 6

Direct Competitor: (continued) Reactions Pro • Appealing because the methodology is an evolutionary approach • Verification Cockpit has nice ease-of-use features supporting the HDL and C++ transactional methods • C can be concise, faster (initial) development time, memory usage efficiency, fastest run time Con • Test. Builder’s “Transaction” / VRM methodology old news - just C++ BFM • C cons: debug and maintenance, crashes, HDL / electrical “services” and constructs lacking • Isn’t this just warmed over C / C++? • Other than NC-Sim integration, what are the advantages vs. Gnu tools? • No advanced test coverage analysis tools or detailed ABV info shown • Low number / medium strength testimonials January 2003 7

Direct Competitor: Products • Gigascale Verification Hub • Quickbench Verification suite • QB Modeler, Sequencer, Manager • RAVE hardware verification language • High-Level Verification Modeling with C++ • System. C Pitch “System. C Interoperability with Verilog & VHDL. And Timing Designer is great. ” Reaction • Confusion - QB Sequencer + RAVE seems to offer a solution • No examples of RAVE, analysis tools? No white papers at all. • Web site inadequate January 2003 8

Direct Competitor: Accellera Products • Open Verification Library - Assertion Templates • System Verilog Assertions • Property Specification Language (Sugar) • EE Times articles Pitch • A promised verification language standard • Verification constructs built into the new Verilog, plus a vendor independent verification language, plus open source checkers. Reaction • Verificationlib. org: tempting to low-end, Sugar, and Mentor customers • Re-play of the Verilog vs. VHDL development story? • Siren song to users in the short term January 2003 9

Formal Verification: Products • Black. Tie Functional Checker • Conformal Logic Equivalence Checker Pitch • Formal verification driven by assertions saves time in two ways: – No test vectors to generate since it’s exhaustive – Run-time faster than simulation • More than just equivalence checking • Independent technology assures an honest audit of your design January 2003 10

Formal Verification: (continued) Reactions Pro • • Outstanding WWW site: “Project Golden Silicon” demos, white papers, testimonials, links, etc. OVL / Accellera leader increases positive perception, long-term interest Strong customer testimonials Novel point: technology independence and verification focus assures an honest audit of your design Con • • Unbelievably Expensive (>=$100 K / seat in PR) (+Training time and $ ? ) Tool’s value is assumed - ROI discussion is avoided completely Synopsys threat increasing: “Formality” tool improving (from SNUG 5/02) Impact of Synopsys acquisition of Co-Design+Superlog? January 2003 11

Formal Verification: Products • Check, Check-Lite, Check-ICE • Search • Checkerware Monitors • Checkware Compiler (User Dev Checkers) • Verification IP Suite (Built-In Checker) Pitch • Assertions & checkers for driving Verilog sim or formal verification Reactions • Mixed message between simulation and Formal Verification methodologies • Verilog only. “Search” feedback tool looks user-hostile. Real test coverage tool? • Reasonable list of Monitors • Non-formal offerings tempting for Verilog simulation users if the price is right January 2003 12

Formal Verification: Product • Solidify Pitch • New FV algorithms faster • No vectors to generate • Exhaustive analysis • ABV with a friendly Verilog-based property syntax Reaction • “Static functional verification” - confusing term • Low Capacity (“up to 20 K gates”) - limited, point tool status • Current language status unclear - proprietary properties or OVL? • One product; one trick pony. Company looks “small”. Is it worth it? January 2003 13

Formal Verification: Products • @Verifier - ABV support • @Designer - debug and analysis Pitch • “Adaptive Functional Verification” is innovative application of Formal Model Checking and Automatic Functional Vector Generation Reaction • Automatic Property Extraction - Really? Does it work? Training? • Point tools - not a comprehensive solution • Advantage of @Designer versus other (built-in) debuggers/viewers? • Open Vera support a plus, but only VCS and NC-Verilog supported • Startup / investor profile (Prabu Goel) worrisome January 2003 14

Other Player(s): Products • Seamless - Co-Simulation • Formal. Pro - FV equivalence checker • All their other tools Pitch • Seamless + other tools are a compelling “substitute” / conventional flow • Formal. Pro growing in interest and adoption (EET anecdotes) Reaction • Mentor is lacking a real ABV / functional verification tool • Formal. Pro could be the kernel of a full formal verification suite • Verisity: devote more resources to grow MGC relationship (Buyout? ) January 2003 15

Observations • Which vendors/tools generated enough interest to consider an eval? – Synopsys, Verplex, 0 -In (+Verisity) • Winning WWW characteristics: useful graphics, white papers, testimonials, code examples, demo downloads, BBS / User Group access – Verplex, Synopsys, Mentor (+Verisity) • Most threatening award: Synopsys. 2 nd place: Verplex • Cadence: paving the cow path -- not really in ABV at all – Granted: C++ based tools: strong evolutionary appeal – Whenever I see C or C++, I think Gnu tools --> lower perceived value – e / ABVs: “city services” (memory alloc, EE constructs) built-in; worth run time hit • Vertical markets & applications poorly addressed (follow Xilinx’s example) • Few make the extensibility / scalability point like Verisity January 2003 16

Conclusions • Best Formal Verification partner? – Averant has the most to gain – 0 -In tools and the company look stronger – Verplex too expensive • Perception IS reality to customers – “Open” VERA, OVL, Acellera - all sound like a positive trend. – My initial bias: formal ver. tools nice to have/curiosity. Now: worth evaluating. • Holes in Mentor’s product line offer a great strategic opportunity • Recommendations for Verisity – Emphasize leadership (“defacto standard”, “all we do is verification”, “ind. audit”) – Continue to emphasize Verisity’s integration with many Verilog, VHDL, C tools – If the “e” language isn’t the secret sauce 1. ) why hide it? 2. ) proprietary issue – Test coverage analysis is a key differentiator – Developing content for specific to popular vertical applications January 2003 17