AC 7 CO Chipset Increasing Services and Reducing

AC 7 CO Chipset Increasing Services and Reducing Total Cost of Ownership 1

DSL Market Requirements Reduced Costs More subscribers per chipset /chassis New Features Support for new standards Backward Compatibility Support for legacy standards Interoperability High-performance with all CPEs 2

AC 7 Answers Needs of OEMs and Operators Reduced Costs Simplified AC 7 design reduces total cost of ownership (TCO) for operators’ ADSL systems & networks New Features Operators can seamlessly support ADSL 2, ADSL 2+, Annex L and READSL Backward Compatibility AC 7 supports all legacy ADSL standards Interoperability AC 7 offers the industry’s strongest interoperability performance 3

AC 7: New Features, New Integration ”Extending True Density Leadership” Dual AFE on Silicon AC 7 Chipset Parameters Power: <750 m. W Dual AFE on Silicon PCM LVDS Mgmt Utopia 2 / POS-PHY 16 Port Multi-Service DSL Transceiver Area: BOM: Dual AFE on Silicon Dual AFE on Silicon 0. 9 sq. inches/port <$0. 85/port 23 Discretes Interfaces: ü Utopia 2 ü POS (packet over Sonet) PHY ü High Speed Serial (LVDS) ü PCM (pulse code modulation) ü Management Standards: ü ADSL 2, ADSL 2+, READSL ü T 1. 413 i 2, ETSI, G. DMT ü Annex A, B, C, I, J, L 4

CO: Infrastructure Product Integration 16 Port Example Digital Xcvr (x 8) 0. 15μ Mixed Signal Codec (x 8) Line Xcvr (x 1) 42 Discretes Transformer (x 1) ADSL CO Bill of Material AC 5 2 chipsets 20 chips 752 discretes 1. 3 W Shrink Mixed Signal Codec (x 8) Digital Xcvr (x 16) 0. 13μ Single-Chip Complete DSL Modem AFE on a Chip (x 2) Dual Line Xcvr (x 2) 22 Discretes 38 Discretes Transformer (x 1) AC 6 2 chipsets 12 chips 624 discretes 920 m. W AC 7 1 chipset 9 chips 368 discretes <750 m. W 5

All High Density CO Chipsets are Not the Same Legacy Solutions MCM-based Solutions Memory Digital XCVR x 12 Codec x 12 Driver x 2 Digital XCVR x 8 Codec x 8 Hybrid Driver x 1 Digital XCVR, Memory, Codec x 16 Hybrid Analog Signal Traces External Hybrid 23 Components External Hybrid 40 -50 Components/port n n Older Classic Three Chip Architecture Less Silicon/Package Integration External Memory Driver, Codec, Hybrid x 2 n Multi-chip Module – a single package but not one piece of silicon External Memory n Single Channel Driver n n Integrated 2 -chip Solution Analog Signal Trace Elimination Integrated Programmable Hybrid Integrated Memory 6

Extending True Density Competitive Comparison Chip and Die Count Comparisons (48 Port Linecard) TI AC 7 Density Delta Chip 60 Company Die ADI -56% -48% STM -33% GSPN -33% -25% INFN -25% CTLM/BRCM -16% 50 40 61 52 40 40 40 36 Higher Integration Means Lower System Costs § § Fewer PCB Layers Decreased Trace Density Easier Board Routing Fewer Components to Manage * Requires external memory 30 36 36 32 32 27 27 20 ADI* STM x 16/x 0/x 1 x 12/x 4/x 2 GSPN G 24* x 24/x 8/x 2 INFN CTLM / BRCM TI AC 7 x 8/x 4/x 2 x 16/x 0/x 2 x 12/x 2 Digital Chip / Codec Chip / Driver Chip Die Count Chip Count 7

Making DSL Networks Simple “Multi Standard/Multi-Service” Before AC 7 With AC 7 Subscriber #1 • Fully Interoperable • Moderate User • No CPE Change Costs • Globespan CPE • No Operational Expenses • G. dmt Subscriber #2 • Moderate User • Alcatel CPE • T 1. 413 i 2 • • Subscriber #3 • Not Served • ADSL 2+ Ready • Soft “Up-Sell” Market Created • Revenue Potential Increases Subscriber #5 • Light User • Alcatel CPE • G. dmt • Fully Interoperable • No CPE Change Costs • No Operational Expenses Fully Interoperable No CPE Change Cost ADSL 2+ Capable Revenue Potential Increases READSL Ready ADSL 2+ Ready • READSL Ready • Revenue Potential Increases Subscriber #4 • Heavy User • TI AR 7 CPE • ADSL 2 Subscriber #1 Subscriber #2 Subscriber #3 Subscriber #4 6 kft (1. 8 km) 9 kft Subscriber #5 (2. 75 km) 12 kft (3. 6 km) 15 kft (4. 6 km) 15 kft is the typical operator standard serving area. With AC 7, operators can offer ADSL 2+ and READSL plus all users have enhanced upstream capabilities. 8

Total Cost of Ownership Advantage Addressing the DSL Investment Chain AC 7 Advantage OEM Expenses Capital H/W Development • Multiple designs • Board re-spins • CAD resources • Multi-service chipsets • One board for world market • Trace count reductions • System costs • Linecard costs • Separate service cards S/W Development • Managing Multiple API’s • Common API w/previous & future chipsets • Advanced analog built in self test • Truck rolls • Interop problems • 33% reduction in chip count • 23 passives/port • Broad interoperability testing • Multi-standard support Operational • Network level electricity draw Operational • Purchasing • Inspection • Inventory • Assembly • Most integrated chipset • Lowest system cost enabled • Multi-service linecards Provisioning Testing • Board debug AC 7 Advantage Service Provider Expenses • Lowest power consumption Maintenance • Fault isolation • Modem stability • Failure rates • ADSL 2: DELT • Interoperability stability • Fewer linecard potential failure points 9

Offering Superior End-to-End Interoperability is the fundamental requirement for all operators worldwide Over 225 CPEs and 30+ DSLAMs can be tested against in TI’s DSL interoperability lab TI’s world-class interoperability lab delivers: § Automated testing with latest § § deployed equipment Database for test data storage and comparisons Operator reports, TI SW release interoperability reports TI’s interop lab facility shortens manufacturer and operator qualification cycle 10

AC 7: Summary Simplified Design Reduces Total Cost of Ownership ADSL, ADSL 2+, Annex L, READSL Support Backward Compatibility with Legacy CPEs Industry Leading Interoperability 16 Port Multi-Service/Multi-Standard Chipset Integration on Silicon -- True 2 -Chip Solution <750 m. W/port, 23 Discretes/port 11

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AC 7 versus Broadcom (w/ Intersil) Board Complexity Comparison (48 Port Example) Broadcom Driver x 2 DSP x 12 Codec x 12 Driver x 2 Hybrid Driver x 2 Hybrid Driver x 2 DSP x 12 Codec x 12 Driver x 2 DSP x 12 Hybrid Driver x 2 Hybrid Hybrid Hybrid Hybrid TI AC 7 Driver x 2 Hybrid Driver x 2 Hybrid Driver x 2 Hybrid Driver x 2 Hybrid Integrated Hybrid (BOM $, Manufacturing) Advantage TI Hybrid DSP x 16 Hybrid Codec Integration (PCB, Inventory) Advantage TI DSP x 16 Hybrid Codec x 12 Analog Signal Trace Elimination (PCB, Debug) Advantage TI Codec x 12 Hybrid Driver x 2 Hybrid Driver x 2 Codec x 12 Programmable Hybrid (Performance) Advantage TI Hybrid DSP x 12 Codec x 12 Driver x 2 DSP x 16 Hybrid Driver x 2 Hybrid 32 Chip Count -27 (Inventory, Manufacturing) Advantage TI Hybrid Driver x 2 Hybrid 13 Hybrid Hybrid Hybrid Driver x 2 Hybrid Driver x 2 Hybrid Driver x 2 Hybrid Hybrid Hybrid Hybrid

AC 7 versus Centillium Maximus w/Intersil) Board Complexity Comparison (48 Port Example) Centillium Maximus Driver x 2 DSP x 12 Codec x 12 Driver x 2 Hybrid Driver x 2 Hybrid Driver x 2 DSP x 12 Codec x 12 Driver x 2 DSP x 12 Hybrid Driver x 2 Hybrid Hybrid Hybrid Hybrid Driver x 2 Hybrid Driver x 2 Hybrid Driver x 2 Hybrid Codec x 12 Hybrid Integrated Hybrid (BOM $, Manufacturing) Advantage TI Hybrid Programmable Hybrid (Performance) Advantage TI DSP x 12 DSP x 16 Codec x 12 Hybrid Hybrid Codec Integration (PCB, Inventory) Advantage TI Analog Signal Trace Elimination (PCB, Debug) Advantage TI DSP x 16 Codec x 12 Driver x 2 Hybrid Driver x 2 Hybrid Driver x 2 DSP x 16 Hybrid Driver x 2 32 Chip Count -27 (Inventory, Manufacturing) Advantage TI Hybrid Driver x 2 TI AC 7 Hybrid Driver x 2 Hybrid 14 Hybrid Hybrid Hybrid Driver x 2 Hybrid Driver x 2 Hybrid Driver x 2 Hybrid Hybrid Hybrid Hybrid

AC 7 versus GSPN G 24 (w/Intersil) Board Complexity Comparison (48 Port Example) Globespan G 24 Driver x 2 Codec x 8 DSP X 24 (MCM) SRAM Codec x 8 (MCM) SRAM Hybrid Driver x 2 Hybrid Hybrid Driver x 2 Codec x 8 DSP X 24 Driver x 2 Hybrid Codec x 8 Hybrid Driver x 2 Hybrid Hybrid Driver x 2 Hybrid Driver x 2 Hybrid Driver x 2 TI AC 7 36 Chip Count -27 (Inventory, Manufacturing) Advantage TI Hybrid Driver x 2 Hybrid Driver x 2 Hybrid SRAM DSP x 16 Programmable Hybrid (Performance) Advantage TI Hybrid Driver x 2 Integrated Hybrid (BOM $, Manufacturing) Advantage TI Hybrid Driver x 2 SRAM Hybrid Codec x 8 Hybrid Hybrid YES MCM NO (Board Reliability) Advantage TI Codec Integration (PCB, Inventory) Advantage TI DSP x 16 SRAM Hybrid DSP x 16 Analog Signal Trace Elimination (PCB, Debug) Advantage TI SRAM Codec x 8 Hybrid Driver x 2 Hybrid Driver x 2 Hybrid Driver x 2 Hybrid 15 Hybrid Hybrid Hybrid Driver x 2 Hybrid Driver x 2 Hybrid Driver x 2 Hybrid Hybrid Hybrid Hybrid

AC 7 versus Infineon Board Complexity Comparison (48 Port Example) Infineon DSP X 8 DSP X 8 Codec x 4 Driver x 2 TI AC 7 Hybrid Codec x 4 Driver x 2 Hybrid Codec x 4 Codec x 4 Codec x 4 Driver x 2 Hybrid Hybrid Driver x 2 Hybrid Hybrid Driver x 2 Hybrid Driver x 2 Hybrid 42 Chip Count -27 (Inventory, Manufacturing) Advantage TI Hybrid DSP X 8 Hybrid Driver x 2 Hybrid Driver x 2 Hybrid DSP x 16 Hybrid Driver x 2 Integrated Hybrid (BOM $, Manufacturing) Advantage TI Hybrid Programmable Hybrid (Performance) Advantage TI DSP x 16 Hybrid Hybrid DSP X 8 Codec Integration (PCB, Inventory) Advantage TI Analog Signal Trace Elimination (PCB, Debug) Advantage TI DSP x 16 DSP X 8 Codec x 4 Driver x 2 Hybrid Codec x 4 Driver x 2 Hybrid Codec x 4 Driver x 2 Hybrid Codec x 4 16 Hybrid Hybrid Hybrid Driver x 2 Hybrid Driver x 2 Hybrid Driver x 2 Hybrid Hybrid Hybrid Hybrid

World’s Best End to End Solution ”AC 7 and AR 7” Legacy ADSL AC 7 x 16 x 2 x 2 ATM or Multi-Protocol Aggregation AC 7 x 16 x 2 x 2 48 Port Linecard ADSL 2 READSL 2+ Annex I, J x 2 x 2 AR 7 Single-Chip DSL Router DELT 802. 11 a/b/g x 2 PCI TI Power Supply Flexible CPE Services & I/F’s VLYNQ Local Loop Services USB 10/100 Central Office • Most Integrated CO Chipset • World’s Most Integrated CPE Chipset • Highly Flexible CO and CPE Service Offerings • LVDS Port Enables Low Cost Aggregation • End to End ATM or Ethernet Operation • Complete Reference Designs • Most Interoperable Solutions ATM Cells Packets 17 Video Data Vo. IP Security

AC 7: System Cost Reductions Today’s Signal Trace Topology Utopia 2 Dual Driver Data Mgmt Dual Driver 8 Port Codec 8 Port Xcvr Clock/ Control Traces Dual Driver Analog Traces Utopia 2 Data 8 Port Codec Mgmt Clock/ Control Traces I/F #1: Digital I/F #2: Digital Three Signal Interfaces #1 Digital – Parallel #2 Digital – Serial #3 Analog – Differential Issues • Too Many Traces Dual Driver 8 Port Xcvr Description • Complex Routing Dual Driver • Higher PCB Costs Dual Driver • Analog Traces susceptible to noise Dual Driver • Parallel interfaces increase FPGA/ASIC costs I/F #3: Analog 18

AC 7: 10 x Reduction in Trace Count “Signal Serialization & Analog Signal Trace Elimination” x 2 x 2 LVDS Serial I/F 622 Mbps 16 Port Multi. Service Xcvr x 2 x 2 x 2 Feature Two Signal Interfaces #1 Digital – Serial #2 Digital – Serial #3 Analog – Internal Option to completely serialize all signal traces Benefit • No Analog Signal Traces • Decreases Routing Density (Less Traces/Unit Area) • Lowers PCB costs • Simplifies board layout I/F #1: Serial I/F #2: Serial • Reduces ASIC/FPGA pin count 19

AC 7: Total Cost of Ownership Impact Total Lifetime Component Count Analysis: - AC 7 has almost 50 M fewer parts than typical competitor - Improves board level and overall product reliability probability - Reduces service and maintenance call probability - Reduces manufacturing complexity 20

AC 7: Total Cost of Ownership Impact Cumulative Lifetime Chipset Assembly Costs Conclusions: - Yields a savings of ~$0. 50/port for all scenarios 21

AC 7: Total Cost of Ownership Impact Fewer Devices to Order, Inventory, & Manage Assumptions: - 3, 000 port product lifetime 22

AC 7: Impacting Operator’s OPEX budgets Network Level Electricity Savings Assumptions: - 3, 000 port network, All modems active 24 hours/day, 365 days/year, full power, $0. 10 k. Wh - Scenario #1: 1. 1 W versus 0. 85 W (AC 7), - Scenario #2: 2. 5 W versus 0. 85 W (AC 7) 23

Building on the Success of ADSL Add New Services with Legacy CPE Protection Legacy CPE Interoperability Maintained 50 M Chipset Phase I: 1. G. lite Only 35 M 30 M Chipset Phase III: 1. ADSL 2, ADSL 2+, READSL 2. Scalable up to 24 Mbps down 3. Scalable up to 3. 8 Mbps up 4. Increased reach 5. Legacy Interoperable w/CPEs in the field Legacy CPE Interoperability Maintained 25 M 24 Mbps 20 M 15 M IV CPE Interoperability Maintained 10 M III 8 Mbps 5 M 1. 5 Mbps II I 896 kbps Extended Reach Area 896 kbps 2 M Upstream Chipset Phase IV: 1. VDSL/ADSL 2. Scalable up to 50+Mbps down 3. Scalable up to 20+Mbps up 2. Legacy Interoperable w/CPEs in the field Downstream Chipset Phase II: 1. G. dmt/G. lite 2. Legacy Interoperable w/CPEs in the field 3. 8 Mbps 4 M 20 M 24