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4446 Design of Microprocessor-Based Systems I/O System Design Dr. Esam Al_Qaralleh CE Department Princess 4446 Design of Microprocessor-Based Systems I/O System Design Dr. Esam Al_Qaralleh CE Department Princess Sumaya University for Technology 1

Introduction (cont’d) q 65, 536 possible I/O ports q Data transfer between ports and Introduction (cont’d) q 65, 536 possible I/O ports q Data transfer between ports and the processor is over data bus q 8088 uses address bus A[15: 0] to locate an I/O port q AL (or AX) is the processor register that takes input data (or provide output data) Data bus AL AX I/O I/O 8088 Address bus A[15: 0] 2

Introduction • I/O devices serve two main purposes – To communicate with outside world Introduction • I/O devices serve two main purposes – To communicate with outside world – To store data • I/O controller acts as an interface between the systems bus and I/O device – Relieves the processor of low-level details – Takes care of electrical interface • I/O controllers have three types of registers – Data – Command – Status 3

Introduction (cont’d) 4 Introduction (cont’d) 4

Introduction (cont’d) • To communicate with an I/O device, we need – Access to Introduction (cont’d) • To communicate with an I/O device, we need – Access to various registers (data, status, …) • This access depends on I/O mapping – Two basic ways » Memory-mapped I/O » Isolated I/O – A protocol to communicate (to send data, …) • Three types – Programmed I/O – Direct memory access (DMA) – Interrupt-driven I/O 5

Accessing I/O Devices • I/O address mapping – Memory-mapped I/O • Reading and writing Accessing I/O Devices • I/O address mapping – Memory-mapped I/O • Reading and writing are similar to memory read/write • Uses same memory read and write signals • Most processors use this I/O mapping – Isolated I/O • Separate I/O address space • Separate I/O read and write signals are needed • Pentium supports isolated I/O FFFFF – 64 KB address space » Can be any combination of 8 -, 16 - and 32 -bit I/O ports – Also supports memory-mapped I/O FFFFF Memory addressing space 00000 I/O FFFF I/O addressing 0000 space Direct I/O 00000 Memory addressing space Memory-mapped I/O 6

Accessing I/O Devices (cont’d) • Accessing I/O ports in 80 x 86 – Register Accessing I/O Devices (cont’d) • Accessing I/O ports in 80 x 86 – Register I/O instructions in accumulator, port 8 ; direct format – Useful to access first 256 ports in accumulator, DX ; indirect format – DX gives the port address – Block I/O instructions • ins and outs – Both take no operands---as in string instructions • ins: port address in DX, memory address in ES: (E)DI • outs: port address in DX, memory address in ES: (E)SI • We can use rep prefix for block transfer of data 7

8088 Port Addressing Space q Accessing directly by instructions IN AL, 80 H IN 8088 Port Addressing Space q Accessing directly by instructions IN AL, 80 H IN AX, 6 H OUT 3 CH, AL OUT 0 A 0 H, AX FFFF Accessed through DX 00 FF 00 F 8 Accessed directly by instructions q Accessing through DX IN AL, DX IN AX, DX OUT DX, AL OUT DX, AX 0000 8

Input Port Implementation Data Bus 8088 Gating device Address bus Input Decoder Other control Input Port Implementation Data Bus 8088 Gating device Address bus Input Decoder Other control signals — The outputs of the gating device are high impedance when the processor is not accessing the input port — When the processor is accessing the input port, the gating device transfers input data to CPU data bus — The decoding circuit controls when the gating device has high impedance output and when it transfers input data to data bus 9

Input Port Implementation q Circuit Implementation — Assume that the address of the input Input Port Implementation q Circuit Implementation — Assume that the address of the input port is 9 CH A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 Data bus Tri-state buffer Input data CE RD IO/M 10

Input Port Implementation 11 Input Port Implementation 11

Output Port Implementation q Circuit Implementation — Assume that the address of the output Output Port Implementation q Circuit Implementation — Assume that the address of the output port is 9 CH A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 Data bus Latch Output data CLK WR IO/M 12

Output Port Implementation 13 Output Port Implementation 13

A Reconfigurable Port Decoder 1 A 7 A 6 A 5 A 4 A=B A Reconfigurable Port Decoder 1 A 7 A 6 A 5 A 4 A=B B 3 A 3 B 2 A 2 B 1 A 1 B 0 A 0 Vcc R A=B A 3 A 2 A 1 A 0 A=B B 3 A 3 B 2 A 2 B 1 A 1 B 0 A=B RD or WR IO/M 14

An Example I/O Device • Keyboard – Keyboard controller scans and reports – Key An Example I/O Device • Keyboard – Keyboard controller scans and reports – Key depressions and releases • Supplies key identity as a scan code – Scan code is like a sequence number of the key » Key’s scan code depends on its position on the keyboard » No relation to the ASCII value of the key – Interfaced through an 8 -bit parallel I/O port • Originally supported by 8255 programmable peripheral interface chip (PPI) 15

An Example I/O Device (cont’d) • 8255 PPI has three 8 -bit registers • An Example I/O Device (cont’d) • 8255 PPI has three 8 -bit registers • Port A (PA) • Port B (PB) • Port C (PC) – These ports are mapped as follows 8255 register PA (input port) PB (output port) PC (input port) Command register Port address 60 H 61 H 62 H 63 H 16

An Example I/O Device (cont’d) Mapping of 8255 I/O ports 17 An Example I/O Device (cont’d) Mapping of 8255 I/O ports 17

An Example I/O Device (cont’d) • Mapping I/O ports is similar to mapping memory An Example I/O Device (cont’d) • Mapping I/O ports is similar to mapping memory – Partial mapping – Full mapping • Keyboard scan code and status can be read from port 60 H – 7 -bit scan code is available from • PA 0 – PA 6 – Key status is available from PA 7 • PA 7 = 0 – key depressed • PA 0 = 1 – key released 18

I/O Data Transfer • Data transfer involves two phases – A data transfer phase I/O Data Transfer • Data transfer involves two phases – A data transfer phase • It can be done either by – Programmed I/O – DMA – An end-notification phase • Programmed I/O • Interrupt • Three basic techniques – Programmed I/O – DMA – Interrupt-driven I/O 19

I/O Data Transfer (cont’d) • Programmed I/O – Done by busy-waiting • This process I/O Data Transfer (cont’d) • Programmed I/O – Done by busy-waiting • This process is called polling • Example – Reading a key from the keyboard involves • Waiting for PA 7 bit to go low – Indicates that a key is pressed • Reading the key scan code • Translating it to the ASCII value • Waiting until the key is released 20

8255 Programmable Peripheral Interface 21 8255 Programmable Peripheral Interface 21

8255 Programmable Peripheral Interface Data bus A 0 A 1 RD WR RESET 8088 8255 Programmable Peripheral Interface Data bus A 0 A 1 RD WR RESET 8088 A 7 A 6 A 5 A 4 A 3 A 2 IO/M D[7: 0] PA[7: 0] PB[7: 0] Control port PC[7: 0] CS A 1 A 0 0 1 1 0 1 1 Port PA PB PC Control 22

8255 Programmable Peripheral Interface 23 8255 Programmable Peripheral Interface 23

Programming 8255 q 8255 has three operation modes: mode 0, mode 1, and mode Programming 8255 q 8255 has three operation modes: mode 0, mode 1, and mode 2 24

Programming 8255 q Mode 0: — Ports A, B, and C can be individually Programming 8255 q Mode 0: — Ports A, B, and C can be individually programmed as input or output ports — Port C is divided into two 4 -bit ports which are independent from each other q Mode 1: — Ports A and B are programmed as input or output ports — Port C is used for handshaking PC 4 PC 5 PC 3 8255 PC 2 PC 1 PC 0 PC 6, 7 PA[7: 0] STBA IBFA INTRA PB[7: 0] STBB IBFB INTRB PC 7 PC 6 PC 3 PA[7: 0] OBFA ACKA INTRA PC 2 PC 1 PC 0 PB[7: 0] OBFB ACKB INTRB 8255 PC 4, 5 25

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Programming 8255 q Mode 2: — Port A is programmed to be bi-directional — Programming 8255 q Mode 2: — Port A is programmed to be bi-directional — Port C is for handshaking — Port B can be either input or output in mode 0 or mode 1 PA[7: 0] 8255 PC 7 PC 6 PC 4 PC 5 PC 3 PC 0 OBFA ACKA STBA IBFA INTRA In Out STBB OBFB IBFB ACKB INTRB PB[7: 0] 1. 2. Mode 1 Mode 0 Can you design a decoder for an 8255 chip such that its base address is 40 H? Write the instructions that set 8255 into mode 0, port A as input, port B as output, PC 0 -PC 3 as input, PC 4 -PC 7 as output ? 28

Timing diagram is a combination of the Mode 1 Strobed Input and Mode 1 Timing diagram is a combination of the Mode 1 Strobed Input and Mode 1 Strobed Output Timing diagrams. 29

Example: Mode 1 Input keyboard 8255 PA 0 • BIT 5 EQU • PORTC Example: Mode 1 Input keyboard 8255 PA 0 • BIT 5 EQU • PORTC • PORTA 20 H EQU • READ • Read: PROC NEAR – – IN AL, PORTC TEST AL, BIT 5 JZ Read IN AL, PORTA • READ 22 H 20 H PA 7 STB PC 4 DAV ; read portc ; test IBF ; if IBF=0 ; Read Data ENDP 30

Example: Mode 1 output Printer 8255 PB 0 PB 7 ACK PC 2 PC Example: Mode 1 output Printer 8255 PB 0 PB 7 ACK PC 2 PC 4 ACK DS Data Strobe : to tell the printer to latch the incoming data. Generated Externally 31

Example: Mode 1 output BIT 1 EQU PORTC PORTB CMD EQU PRINT PROC 2 Example: Mode 1 output BIT 1 EQU PORTC PORTB CMD EQU PRINT PROC 2 EQU 62 H EQU 61 H 63 H NEAR ; check printer ready? IN AL, PORTC ; get OBF TEST AL, BIT 1 ; test OBF JZ PRINT ; if OBF=0 buffer is full ; send character to printer MOV AL, AH ; get data OUT PORTB, AL ; print data ; send data strobe to printer MOV AL, 8 ; clear DS OUT CMD, AL MOV AL, 9 ; clear DS OUT CMD, AL ; rising the data at the positive edge of DS RET PRINT ENDP 32

Keyboard example 1/2 33 Keyboard example 1/2 33

Keyboard example 2/2 34 Keyboard example 2/2 34

Bouncing Problem 35 Bouncing Problem 35

Bouncing 36 Bouncing 36

Software Solution 37 Software Solution 37

De-bouncing Circuitry Two asynchronous flip-flop solutions are given below • The basic idea is De-bouncing Circuitry Two asynchronous flip-flop solutions are given below • The basic idea is that these flip-flops store the values even if the D/D nodes both float 38

Another Solution 39 Another Solution 39

External Interface • Two ways of interfacing I/O devices – Serial • Cheaper • External Interface • Two ways of interfacing I/O devices – Serial • Cheaper • Slower – Parallel • Faster • Data skew • Limited to small distances 40

External Interface (cont’d) Two basic modes of data transmission 41 External Interface (cont’d) Two basic modes of data transmission 41

External Interface (cont’d) • Serial transmission – Asynchronous • Each byte is encoded for External Interface (cont’d) • Serial transmission – Asynchronous • Each byte is encoded for transmission – Start and stop bits • No need for sender and receiver synchronization – Synchronous • Sender and receiver must synchronize – Done in hardware using phase locked loops (PLLs) • Block of data can be sent • More efficient – Less overhead than asynchronous transmission • Expensive 42

External Interface (cont’d) 43 External Interface (cont’d) 43

External Interface (cont’d) Asynchronous transmission 44 External Interface (cont’d) Asynchronous transmission 44

External Interface (cont’d) • EIA-232 serial interface – Low-speed serial transmission – Adopted by External Interface (cont’d) • EIA-232 serial interface – Low-speed serial transmission – Adopted by Electronics Industry Association (EIA) • Popularly known by its predecessor RS-232 – It uses a 9 -pin connector DB-9 • Uses 8 signals – Typically used to connect a modem to a computer 45

External Interface (cont’d) • Transmission protocol uses three phases – Connection setup • Computer External Interface (cont’d) • Transmission protocol uses three phases – Connection setup • Computer A asserts DTE (Data Terminal Equipment) Ready – Transmits phone# via Transmit Data line (pin 2) • Modem B alerts its computer via Ring Indicator (pin 9) – Computer B asserts DTE Ready (pin 4) – Modem B generates carrier and turns its DCE (Data Communication Equipment) Ready • Modem A detects the carrier signal from modem B – Modem A alters its computer via Carrier Detect (pin 1) – Turns its DCE Ready – Data transmission • Done by handshaking using – request-to-send (RTS) and clear-to-send (CTS) signals – Connection termination • Done by deactivating RTS 46

External Interface (cont’d) • Parallel printerface – A simple parallel interface – Uses 25 External Interface (cont’d) • Parallel printerface – A simple parallel interface – Uses 25 -pin DB-25 • 8 data signals – Latched by strobe (pin 1) • Data transfer uses simple handshaking – Uses acknowledge (CK) signal » After each byte, computer waits for ACK • 5 lines for printer status – Busy, out-of-paper, online/offline, autofeed, and fault • Can be initialized with INIT – Clears the printer buffer and resets the printer 47

External Interface (cont’d) 48 External Interface (cont’d) 48

Serial Data Transfer q Asynchronous v. s. Synchronous — Asynchronous transfer does not require Serial Data Transfer q Asynchronous v. s. Synchronous — Asynchronous transfer does not require clock signal. However, it transfers extra bits (start bits and stop bits) during data communication — Synchronous transfer does not transfer extra bits. However, it requires clock signal Frame Asynchronous Data transfer Synchronous Data transfer data Start bit B 0 B 1 B 2 B 3 B 4 B 5 B 6 Stop bits Parity clk data B 0 B 1 B 2 B 3 B 4 B 5 Baud (Baud is # of bits transmitted/sec, including start, stop, data and parity). 49

8251 USART Interface 8251 D[7: 0] RS 232 Tx. D RD WR A 0 8251 USART Interface 8251 D[7: 0] RS 232 Tx. D RD WR A 0 RD WR C/D CLK Rx. D Tx. C Rx. C A 7 A 6 A 5 A 4 A 3 A 2 A 1 IO/M 50

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Programming 8251 q 8251 mode register 7 6 Number of Stop bits 00: invalid Programming 8251 q 8251 mode register 7 6 Number of Stop bits 00: invalid 01: 1 bit 10: 1. 5 bits 11: 2 bits 5 4 3 2 0 Mode register Baud Rate Parity enable 0: disable 1: enable Character length Parity 0: odd 1: even 1 00: Syn. Mode 01: x 1 clock 10: x 16 clock 11: x 64 clock 00: 5 bits 01: 6 bits 10: 7 bits 11: 8 bits 52

Programming 8251 q 8251 command register EH IR RTS ER SBRK Rx. E DTR Programming 8251 q 8251 command register EH IR RTS ER SBRK Rx. E DTR Tx. E command register Tx. E: transmit enable DTR: data terminal ready, DTR pin will be low Rx. E: receiver enable SBPRK: send break character, Tx. D pin will be low ER: error reset RTS: request to send, CTS pin will be low IR: internal reset EH: enter hunt mode 53

Programming 8251 q 8251 status register DSR SYNDET FE Tx. RDY: Rx. RDY: Tx. Programming 8251 q 8251 status register DSR SYNDET FE Tx. RDY: Rx. RDY: Tx. EMPTY: PE: OE: FE: SYNDET: DSR: OE PE Tx. EMPTY Rx. RDY Tx. RDY status register transmit ready receiver ready transmitter empty parity error overrun error framing error sync. character detected data set ready 54

Simple Serial I/O Procedures q Read q Write start Check Rx. RDY Check Tx. Simple Serial I/O Procedures q Read q Write start Check Rx. RDY Check Tx. RDY Is it logic 1? No Is it logic 1? Yes Read data register* end * This clears Rx. RDY No Yes Write data register* end * This clears Tx. RDY 55

Errors – Parity error: Received data has wrong error -- transmission bit flip due Errors – Parity error: Received data has wrong error -- transmission bit flip due to noise. – Framing error: Start and stop bits not in their proper places. • This usually results if the receiver is receiving data at the incorrect baud rate. – Overrun error: Data has overrun the internal receiver FIFO buffer. • Software is failing to read the data from the FIFO. 56

Programmable Timer 8254 57 Programmable Timer 8254 57

8254 Programming 58 8254 Programming 58

8254 Programming • Each counter may be programmed with a count of 1 to 8254 Programming • Each counter may be programmed with a count of 1 to FFFFH. – Minimum count is 1 all modes except 2 and 3 with minimum count of 2. • Each counter has a program control word used to select the way the counter operates. – If two bytes are programmed, then the first byte (LSB) stops the count, and the second byte (MSB) starts the counter with the new count. 59

8254 Read Back Command q 8254 Read Back Command 1 1 COUNT STATUS CNT 8254 Read Back Command q 8254 Read Back Command 1 1 COUNT STATUS CNT 2 CNT 1 CNT 0 0 M 1 M 0 BCD q 8254 status word format NULL OUTPUT COUNT RW 1 RW 0 M 2 NULL COUNT: goes low when the new count written to a counter is actually loaded into the counter 60

8254 Modes • Mode 0: An events counter enabled with G. – The output 8254 Modes • Mode 0: An events counter enabled with G. – The output becomes a logic 0 when the control word is written and remains there until N plus the number of programmed counts. Mode 1: One-shot mode. – – The G input triggers the counter to output a 0 pulse for `count' clocks. Counter reloaded if G is pulsed again. 61

8254 Modes • Mode 2: Counter generates a series of pulses 1 clock pulse 8254 Modes • Mode 2: Counter generates a series of pulses 1 clock pulse wide. – The seperation between pulses is determined by the count. – The cycle is repeated until reprogrammed or G pin set to 0. – Mode 3: Generates a continuous square-wave with G set to 1. • If count is even, 50% duty cycle otherwise OUT is high 1 cycle longer. 62

8254 Modes • Mode 4: Software triggered one-shot – (G must be 1). • 8254 Modes • Mode 4: Software triggered one-shot – (G must be 1). • Mode 5: Hardware triggered one-shot. G controls similar to Mode 1. 63

Motor Control 64 Motor Control 64

Motor Control 65 Motor Control 65

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DMA • Direct memory access (DMA) – Problems with programmed I/O • Processor wastes DMA • Direct memory access (DMA) – Problems with programmed I/O • Processor wastes time polling – In our example » Waiting for a key to be pressed, » Waiting for it to be released • May not satisfy timing constraints associated with some devices – Disk read or write – DMA • Frees the processor of the data transfer responsibility 67

DMA Example • A hard disk data transfer rate of 5 MB/s – One DMA Example • A hard disk data transfer rate of 5 MB/s – One byte every 200 ns !! • A microprocessor hardly can execute even one instruction in 200 ns. – Multiple instructions would be required to accomplish data transfer • • read the byte from the hard disk place it in memory increment a memory pointer test for another byte to read 68

DMA 69 DMA 69

DMA • DMA is implemented using a DMA controller – DMA controller • Acts DMA • DMA is implemented using a DMA controller – DMA controller • Acts as slave to processor • Receives instructions from processor • Example: Reading from an I/O device – Processor gives details to the DMA controller » I/O device number » Main memory buffer address » Number of bytes to transfer » Direction of transfer (memory I/O device, or vice versa) 70

DMA • Steps in a DMA operation – Processor initiates the DMA controller • DMA • Steps in a DMA operation – Processor initiates the DMA controller • Gives device number, memory buffer pointer, … – Called channel initialization • Once initialized, it is ready for data transfer – When ready, I/O device informs the DMA controller • DMA controller starts the data transfer process – – – Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read, loops back to repeat the process – Notify the processor when done • Typically uses an interrupt 71

I/O Data Transfer (cont’d) DMA controller details 72 I/O Data Transfer (cont’d) DMA controller details 72