3 D ICs The Next Revolution Ho-Ming Tong

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3 D ICs: The Next Revolution Ho-Ming Tong GM & Chief R&D Office Group R&D December, 2009

“You Can Resist An Invading Army; You Cannot Resist An Idea Whose Time Has Come, ” Victor Hugo, French Author of • The Hunchback of Notre Dame • Les Misérables 19 th Century France First Republic Napoléon Bonaparte (Napoléon Ier) 1800 Third Republic Second Republic 1810 Louis XVIII Charles X 1820 1830 Louis-Philippe Ier 1840 Louis-Napoléon Bonaparte (Napoléon III) 1850 1860 1870 Victor Hugo (1802 -1885) © ASE Group. All Rights Reserved. 2 1880 1900

Disruptive Low-power & High Performance Technology Required 2. 0 Perf / Watt (au) 130 nm 1. 7 150 nm Goal 1. 4 250 nm 90 nm 1. 1 65 nm 45 nm 350 nm 0. 8 W. Haeosch et al IBM J. R & D. (2006) 0. 5 10 100 1, 000 Lg (nm) Performance Improvement At The Expense of Power © ASE Group. All Rights Reserved. 9

3 D IC is Next Revolution in Semiconductor & Package Technology Roadmaps Better Performance Ø Massive Bandwidth Ø Reduced Interconnect Delays Ø Power Reduction Ø Higher Functionality/Space Ø Heterogeneous Integration Photonics MEMS Smaller Size Ø 3 D Maximizes Space Utilization RF Memory CMOS Lower Cost Ø Lower Cost vs. Next-gen Device Ø Reuse of Proven SIP © ASE Group. All Rights Reserved. 13

3 D Si. P Evolution Finer Pitch WLCSP FO-WLP Si. P Heterogeneous Integration IC + Assembly Wirebond BGA Wireless Proximity FC BGA 3 D IC - Capacitive - Inductive Stacked Die Po. P 2. 5 D IC EPS (Si Interposer) Heterogeneous Integration Assembly + Substrate © ASE Group. All rights reserved. 15

3 D Si. P Benchmarking: 2. 5 D IC Available Before 3 D IC Performance Stacked Die Fair FO-WLP Fair 2. 5 D IC Good So. C Good 3 D IC Excellent Process Supply Chain (Assy+Test) Fair Po. P EDA Ready Existing Infrastructure Now - ‘ 10 ’ 11 - ‘ 12 ‘ 11 ‘ 12 Year Ready by Year © ASE Group. All Rights Reserved. 18

IC-package-system Compatibility Key to 2. 5 D & 3 D ICs Applications High 2. 5 & 3 D ICs w/ TSVs GPU, Chipset & FPGA Networking Application Processor Chip Size Memory Baseband BT/Wi. Fi rs LK U K/ EL PM Transceiver PA 45 (≦ fe Wa nm s) e Nod Peripheral I/O Controller Switch Discrete 100 © ASE Group. All rights reserved. 200 300 I/O 500 400 19 600 High

Changing Supply Chains 2. 5 D IC (Si Interposer) 3 D IC (Via First) TSV Fab + TSV Backside Grinding Fab Surface Treatment Bottom Side RDL Rep Top Side RDL + Micro-bump RDL FC Bumping Micro-bump Die Stacking Assembly & Test Front-end © ASE Group. All Rights Reserved. Middle-end = Front-end + Back-end 20

2. 5 D IC: An Alternative to 3 D IC MEMS Memory Processor RF Silicon Interposer l Lower Power l High Performance l Compact Size l Larger X-Y Sizes l Higher Power Consumption Compared to 3 D IC Pros l Integration Flexibility: Device Function Partitioning & Easy Mix & Match of Package Styles l Lower Process Risk l So. C (2 D) Like Integration: More Compatible w/ Current EDA Tool l Ease of Production Planning l Ease of DFT/BIST/DFY l Rework Possibility l Short Development Cycle: TTM l Lower cost l l l l Cons © ASE Group. All Rights Reserved. Complicated Integration Higher Process Risk EDA Tool Support Issue Single Source for Custom IC DFT/BIST Challenges Challenging Rework Longer Development Cycle Time Potentially High Product Cost 22

2. 5 IC Enables Device Function Partitioning for Cost Performance RF Node 2 (> Node 1) RF BB BB Node 1 (= 28 nm) PMU Node 3 (> Node 2) 28 nm 2. 5 D IC (Single-chip Package) © ASE Group. All Rights Reserved. 23 Silicon Interposer

Assembly + Substrate Cost High Substrate Capabilities 2. 5 D IC Bridges The Interconnect Gap Between IC & Substrate L/S Yield* 40/40 µm 30/30 µm 20/20 µm 15/15 µm - 10/10 µm 85% 80~85% 65~75% <65% FC Package Cost SP (Excl. Die) C Substrate 2. 5 D IC Substrate Interposer 1+2+1 Cost Assembly 2 Layer Cost Node 1 > * Base on The Best Substrate Source © ASE Group. All Rights Reserved. Si Interposer Node 2> Node 3> Advanced Wafer Node 25 Node 4 Assembly

2. 5 D & 3 D ICs Revolutionize Existing Advanced Packaging Infrastructure ‘ 09 FAB Technology FC Bump Pitch (µm) 45 nm 150 ‘ 10 45 nm 140 - 80 ‘ 11 Wafer-level L/S (µm/µm) Wafer Probing Pitch (µm) ‘ 13 28 nm 125 - 30 110 - 30 32 nm 125 - 40 µBump D 2 D & D 2 W FC Assembly Substrate L/S (µm) ‘ 12 µFC µWLCSP 25/25 20/20 15/15 10/10 6/6 6/6 70 50 Back. Side 15/15 > 100 © ASE Group. All Rights Reserved. 10/10 80 27 < 50 µSi. P

Innovation Required to Reduce 3 D IC Assembly Cost High Min Pitch/Wafer Thickness Substrate Solutions FC Bum p Pitch Standard Reflow Assembly Cost 2. 5 D IC TSV M icrob Thermal Compression Bonding ump Pitch 3 D IC Max 2007 © ASE Group. All rights reserved. 2008 2009 2010 28 2011

3 D IC Metrology Opportunities Microbump Joint (X-ray) Re-passivation/RDL (August) Memory TSV Depth (IR: FOGALE) X X TSV Depth (SAWLI: STIL) TSV CD (AVI: August) X Processor TSV Plating (X-ray: Dage) X X X TSV Stop-on-metal (E-beam: N/A) Rep/RDL (August) Interface Adhesion (SAT) Solder/Cu Pillar Joint (X-ray) Wafer-level Test (Probe Card) Gap © ASE Group. All rights reserved. Ready 30

3 D IC Yield Y 1 = Joint Yield Memory Y 2 = Repassivation/RDL Yield Y 3 = Interface Yield X X X Processor ELK/ULK Y 4 = TSV Yield Y 5 = Interface Yield Y 6 = Repassivation/RDL Yield X X X RDL Y 7 = Joint Yield X X Y 8 = Joint Yield Y 9 = Substrate Yield Y 10 = Joint Yield Y 1 Y 2 Y 3 Y 4 Y 5 Y 6 Y 7 Y 8 Y 9 Y 10 Overall Yield 99. 5% 99. 5% 95. 0% Scrap or Barely Usable 99. 5% 90. 0% 99. 5% 70. 0% Scrap © ASE Group. All rights reserved. 31

TSV Redundancy Improves Yield Electrical Redundancy Achieved by 7 Bars Assembly Yield (300 TSVs) # Signal TSVs # Redundant TSVs 4 -Die Stack 8 -Die Stack 2/1 95% 76% 4/2 99. 8% 98% Refs. : (Samsung ’ 09) & Shapiro (IBM ’ 09) © ASE Group. All rights reserved. 32

3 D IC Test Challenges & Opportunities RF MEMS l Known Good Die u u Memory l RF/At Speed Digital/IPD Test Coverage TSV Test u u l Finer Pitch (≦ 50 µm, Area Array) Thin Wafer Handling (≦ 100 µm) 3 D IC Integrated Test u u Logic l Test Access System-level Test Yield u Substrate l Optimized Assembly & Test Flow Test Cost u Cost Effective Test Refs. : Verigy, NXP, TI, & ASE Data © ASE Group. All Rights Reserved. 33

3 D IC Equipment Readiness Product Type Wafer Thinning / Grinding Criteria 50 µm Via Etching 20 ~ 50 µm, AR 10 Via Isolation 20 ~ 50 µm, AR 10 Via Seedlayer 20 ~ 50 µm, AR 10 Via Etching Via Last 200 mm Wafer Readiness 300 mm Wafer Readiness 5 ~ 10 µm, AR 10 Via First Via Isolation Via Seedlayer Thin Wafer Handling Via Surface Finish Re-distribution (Double Sides) 5 ~ 10 µm, AR 10 50 µm No Cu Dishing - Micro-bumping 30 µm Pitch TSV Wafer Probing & Testing 30 µm Pitch Wafer Singulation D 2 W/W 2 W Bonding Solder / Micro Bump Assembly - Final Test Ready for Mass Production Ready for Qualification © ASE Group. All rights reserved. Ready for Prototyping No Solution Yet 34

Resolving 3 D IC Thermal Challenges Through IC to System Co-design High Power Density (Source: Intel) 3 D IC • 3 D Floor Planning • Dynamic & Leakage Power Management • 3 D EDA Tool • Thin-film Thermo. Electric Cooler (TFTEC) Challenges Possible Solutions Packaging System • Hot Spots • High Power Density • Micro-channel w/ Nanofluid • Nano Materials Test • Test Socket / Chuck Design • Burn-in Oven Cooling Capacity • Liquid Cooling • Thermo-Electric Cooler (TEC) © ASE Group. All Rights Reserved. 35 • Cooling Capacity • Space Constraint • Noise • Vapor chamber • Liquid Cooling • Thermo-Electric Cooler (TEC) • Refrigeration Cooling

New System Architecture Required for 3 D IC Proliferation v Key: IC-package-system Co-design – System Cost – Software – Performance: Clock Feed & Power Feed – Function Partioning – Chip to Chip Interface Standardization – Supply Chain Complexity: Inventories, Liability & Shipment – Alternative Solutions – Test Coverage & Flow v Hot Issues: Memory Interface & 3 D System Bus Standards Refs. : Laukkala & Kujala (Nokia) & Shapiro (IBM) © ASE Group. All Rights Reserved. 36

P 24 3 D IC Integration Requires Concurrent IC – package - system Co-design for Yield & Reliability Design Entry (RTL) System Partition Physical Implementation (Floor Plan / P&R) IP Reuse Design Entry (RTL) System Architecture Planning & Spec Definition Logic Synthesis (Gate Level Realization) Chip Finishing (DRC/DFM) Chip Fabrication Chip Test Foundry TSV Design Reference Flow Logic Synthesis (Gate Level Realization) PKG Process Risk Assessment & Design Rule Physical Implementation (Floor Plan / P&R ) PKG Perf. Parameter Data base System Software & Firmware Development IC Design House © ASE Group. All Rights Reserved. Wafer foundry Chip Finishing (DRC/DFM) Package Design Assembly Tape Out System Integration Design Assembly & Test 38 Chip Fabrication Chip Test 3 D IC Integration Assembly & Test System Integration Test System & Product

Ensuring Package-system Compatibility Besides Chip-package Compatibility Early Life Performance (ELP) Reliability Test (System-centric) • Junction Temperature & Clamping Pressure History under System Operation Conditions • System Reliability (Single or Multiple Die) Customer Requirements & Customer’s Customer Requirements + • IC Requirements • System Requirements • Hardware to Support System Reliability • Customer QA Requests System-level Board Reliability Modeling (Package-centric) + • Mimic Package-on-board • Power cycling of Package on Board • Thermal & Mechanical Stress Simulations • Clamping Pressure & Junction Temperature Safety Zone Enhanced ELP Reliability Test (System-centric) = Package-on-board Safety Conditions to IC & System Customers © ASE Group. All Rights Reserved. 40

Co-design Critical to Ensure Chip-package-system Compatibility for FCBGA Si Die Underfill Rep Delamination ! ELK/ULK Rep ELK/ULK Layer Crack ! RDL Underfill Bump IMC Crack ! Solder Bump Eutectic Bump Fatigue Resistance ELK/ULK Protection Electromigration Performance Solder Mask Cu Pad BT Core No Longer Dumb Connector © ASE Group. All Rights Reserved. 42 Pb-free Bump (ELK) Cu Pillar (ULK) Good Fair Poor Fair Good

Co-design Also Crucial to 3 D IC for Chip-package-system Compatibility Front-end Memory Back Side Bump Middle-end Back Side Rep or RDL Processor Die w/ TSVs (Via Last) Front-end ELK/ULK Layers Middle-end Substrate Back-end 3 D IC (Via First) Memory + Processor Stack © ASE Group. All Rights Reserved. 43

3 D IC Co-design Challenges & Opportunities 3 D IC RF MEMS Board Memory Analog Passives Controller Interposer + IPD Logic SOC Substrate Challenges Gap Design 3 D IC EDA Tool Environment 3 D IC Design Flow from IC to System Electrical TSV Characterization (Electrical + Stress) System-level SI/PI Validation & Sign-off Flow Thermal 3 D IC Thermal Models Thermally Aware Design & Management Mechanical System-level Package Reliability © ASE Group. All rights reserved. No Proven Product Validation Flow & Tool Support Flow & Tool No Test Standard 44

3 D IC Applications Abound 2010 ~ 2020 (Driver: Better Life) Now l CMOS Image Sensor l Memory l Transportation - Drive to Autonomous Cars - Telematics Infrastructure - SRAM/DRAM - NAND 2020 ~ 2040 l Medical Electronics Application Processor /Baseband CPU - Home Medical l GPU l FPGA l MEMS … l - Diagnostics & Therapy l Security - Video Analytics - Video Intelligence l Green Energy Harvesting - Macro: Solar, Wind & Wave - Micro: Piezoelectric, Kinetic & Thermoelectric - Thin Film Batteries © ASE Group. All rights reserved. Quantum Nucleonic Biofuel Biometics Bionics: - Robo Sapiens - Cognitronics - Genotyping - Imaging l • • 45 • • • Frictionless Vehicles Lab-on-a-chip Molecular Sensor Nonobots Self-illuminating Highway

High • • Transistor Density Si. P Package, Die & System Levels FO-WLP EPS 2. 5 D IC 3 D IC Flexible Circuit MEMS Opto Wireless Proximity ogy More Than Moore • Stacked Die um Brick Wall • Po. P y nt Qua • Bio nol Tech • Molecular og ol hn on So. C c Te ic Sil Component Density Package & Die Levels Package Level High 3 D IC Users in The Era of Heterogeneous Integration Feature Size System Component Density 45 nm 1990 2000 © ASE Group. All rights reserved. 2010 4 nm 2020 46 2030 2040

Implanted Wireless Device World's First ‘Wireless' Pacemaker Talks to your Doctor Daily, Whether You Like It or Not (Though You Probably Do) by Joseph L. Flatley (8/’ 09) © ASE Group. All rights reserved. 47