2012 Component Training Ivy Platform Series Confidential

Ivy 7 Series – Agenda • Platform Structure Ø CPU feature introduce Ø Intel 7 series chipset architecture • • Critical Power Flow Clock Distribution Power Sequence Problem Debug Ø Ø Can’t power on Power auto shutdown All dots, zero, and no display Power part

CPU Feature introduce

Intel 7 Series Chipset Architecture

P 8 Z 77 -V LX Architecture

P 8 Z 77 -V DELUXE Architecture

PCH Feature introduce

Ivy 7 Series – Agenda • Platform Structure Ø CPU feature introduce Ø Intel 7 series chipset architecture • • Critical Power Flow Clock Distribution Power Sequence Problem Debug Ø Ø Can’t power on Power auto shutdown All dots, zero, and no display Power part

P 8 Z 77 -V LX Power Flow

P 8 Z 77 -V DELUXE Power Flow

Ivy 7 Series – Agenda • Platform Structure Ø CPU feature introduce Ø Intel 7 series chipset architecture • • Critical Power Flow Clock Distribution Power Sequence Problem Debug Ø Ø Can’t power on Power auto shutdown All dots, zero, and no display Power part

7 Series Clock Distribution 7 Series due to over clocking, Z 77&H 77 series MB have some difference: Z 77 series MB all use PCH integrate CLK GEN. H 77 series MB usually use external CLK GEN. 12

P 8 Z 77 -V LE Clock Distribution : Can measure the waveform 13

SATA clock 1. If PCH internal provide CLK, it will use two 10 K ohm resistors to connect to ground. 2. If not, external CLK generator will provide 100 M Hz frequency for PCH

External CLK GEN (ICS 9 LRS 4206) Check point: 1. VCC 2. 14 M crystal 3. CK_PG 4. CK_RESET# Refer model: P 8 H 77 -V LE To 14 M_PCH

Ivy 7 Series – Agenda • Platform Structure Ø CPU feature introduce Ø Intel 7 series chipset architecture • • Critical Power Flow Clock Distribution Power Sequence Problem Debug Ø Ø Can’t power on Power auto shutdown All dots, zero, and no display Power part

Power on sequence P 9 X 79 Deluxe - Power Sequence (1) 2 1 SR 107 +BAT_3 V 3 V_ATX S_DSWVRMEN SR 106 S_INTVRMEN SR 79 S_SRTCRST# SR 75 Battery S_RTCRST# 3 4 Power Supply 5 SIO 6 S_RTCRST # O_RSMRST# O 2_RSMRST# 6 S_RTCRST# O_RSMRST# O 2_RSMRST# 7 P_+VTTCCIO_REF_10 P_+1. 8 SFR_REF_10 P_+VCCSA_REF_10 O_PSON# O 2_CUT_PSON# Refer model: P 8 Z 77 -V DELUXE 8 O 2_PSON#

Power on sequence P 9 X 79 Deluxe - Power Sequence (3) Power Button 9 10 SIO O_PWRBTN#IN O_PWRBTN# 12 SLP_S 3# SLP_S 4# 11 SIO 13 O_PSON# O 2_CUT_PSON# 13 14 O 2_PSON# Power Supply 3 V, 5 V, 12 V 15 Power Supply B_ATX_PWROK SIO

Power on sequence

Ivy 7 Series – Agenda • Platform Structure Ø CPU feature introduce Ø Intel 7 series chipset architecture • • Critical Power Flow Clock Distribution Power Sequence Problem Debug Ø Ø Can’t power on Power auto shutdown All dots, zero, and no display Power part

Debug - Can’t power on (1) 1. Check SIO power sequence and working condition: +3 V_BAT +3 VSB_ATX O_IOPWRBTN# (D) PWRBTN# PANEL (B) O_PWRBTN#_R (C) O_RSTCON# O_SKTOCC SLP_S 3# (E) SIO PCH SLP_S 4# (E) O_3 VSBSW# RSMRST# (A) PSON# (F) ATX_PSON# (G)

Debug - Can’t power on (2) 2. Check PCH power sequence and working condition 3. Other condition: make sure 5 V_DUAL & 1. 5 VDUAL is low; 1. 5 V_DUAL phase inductor +3 V_BAT (455) SLP_S 3# +3 VSB (267) (493) PCH SLP_S 4# (493) (560) 32. 768 Crystal S_RTCRST# (560) S_SRTCRST# (560) S_INTVRMEN (560) S_DSWVRMEN (560) 0_RSMRST#_R (516) O_DPWROK (518) (560) *(red part): using multi meter with diode status, red(VΩm. A ) to ground & black to test via

Debug - Can’t power on (3) 4. O_SKTOCC: SIO uses this pin to detect MB with CPU or not. At G 3, before installing CPU, H_SKTOCC# voltage level is high; after installing CPU, H_SKTOCC# signal will get low. +3 V_BAT Status Signal Power level Without installing CPU +3 V_BAT H_SKTOCC# High O_SKTOCC Low H_SKTOCC# Low O_SKTOCC High Installing CPU SIO O_SKTOCC H_SKTOCC# CPU Socket

Debug – Power auto shutdown (1) 1. 2. 3. 4. 5. 6. Update BIOS or exchange another BIOS chipset Make sure that MB has no crack, trace open and components missing or damage Check DMI (or FDI) LED bus signals are ok. Check main voltage impedance. If ok, short with PSON to check main voltage. 12 V/5 V/3 V/5 VDUAL/1. 5 VDUAL/ VTTDDR/1. 05 PCH/1. 8 SFR/VCCSA/ VCCIO/VCORE When power on, BIOS signals will start to receive command & send data. CS# WP# & HOLD CLK MOSI MISO

Debug – Power auto shutdown (2) 7. Follow the sequence, measure that PSON#, SLP_S 3, SLP_S 4, PWRBTN# and RSTCON# are normal or not. +3 V_BAT +3 VSB_ATX O_IOPWRBTN# (D) PWRBTN# PANEL (B) O_PWRBTN#_R (C) SLP_S 3# (E) O_RSTCON# O_SKTOCC SIO PCH SLP_S 4# (E) O_3 VSBSW# Detect 5 V/12 V/VCORE PIN RSMRST# (A) PSON# (F) ATX_PSON# (G)

Debug – Power auto shutdown (2) 10. If PCH working condition is abnormal, MB also will shutdown. 1. 05 ME 1. 05 PCH 1. 8 VSFR VCCIO 3 V 3 VSB VCC_XCKPLL (1. 8 V) VCCDMI_PLL_PCH (1. 05~1. 1 V) O_PWROK (533) S_DRAMPWROK (478) S_CPUPWRGD (440) P_VRMPWRGD (484) S_PLTRST# (275) P_VCORE_SHDN#_10 (480) PCH S_25 M_OUT S_25 M_IN S_ICH_RTCX 1 S_ICH_RTCX 2 CK_100 M_DMIP CK_100 M_DMIN CK_33 M_EPCI CK_33 M_SIO CK_33 M_PCH CK_48 M_SIO S_SMBCLK_MAIN (497) S_SMBDATA_MAIN (497) S_SMBCLK_VSB (487) S_SMBDATA_VSB (497)

Debug – Power auto shutdown (3) Problem with power shutdown: THERMAL signals, voltage, PCH working condition and the power sequence (power ok signals) 8. If H_THERMTRIP# is low, P_VCORE_SHDN#_10 will pull low to PCH. 9. If VCORE is abnormal, VRM IC will also use P_VCORE_SHDN#_10 to pull low. VCCIO +3 V P_VCORE_SHDN#_10 CPU VRM IC PCH H_THERMTRIP#

Debug – All dots, zero, and no display Before 00: 1. Power on 2. Power/CLK/RST 3. CPURST# CPU PCIEX 16 DMI FDI After 00 and CPURST#: 1. CPU to PCH (DMI) 2. PCH to BIOS (SPI) 3. SPI to PCH (SPI) 4. PCH to CPU (DMI) PCH to MEMORY (SMB) 5. CPU to MEMORY 6. PCH to SIO (LPC) PCH to EC 7. PCH to DEVICE 8. CPU to PCH (FDI) 9. PCH to DVI/VGA/HDMI CPU to PCIEX 16 VRM SMB DVI SATA VGA USB HDMI LAN USB 3. 0 Audio SPI LPC SIO O 2_SMB

Debug – All dots, zero, and no display Measure BUS: 1. DMI: H_DMI_RXN/P[0: 3] H_DMI_TXN/P[0: 3] S_DMICOMP S_DMIRBIAS VCCDMI_PLL_PCH 2. FDI: H_FDI_INT H_FDI_COMP H_FDI_FSYNC[0: 1] H_FDI_LSYNC[0: 1] H_FDI_TXN/P[0: 7] D 3 A_CLKP/N[0: 1] D 3 A_CS#[0: 1] D 3 A_ODT[0: 1] D 3 A_CKE[0: 1] D 3 A_WE# D 3 A_RAS# D 3 A_CAS# DMI 4. Memory to CPU D 3 A_DQ[0: 63] D 3 A_MA[0: 15] D 3 A_DQSN/P[0: 7] D 3 A_BA[0: 2] D 3_RESET# FDI 3. SMB: S_SMBCLK_MAIN S_SMBDATA_MAIN S_SMBCLK_PCI S_SMBDATA_PCI CPU SMB

Debug – All dots, zero, and no display Chipset (EC C. SEPT 036) F_FRAME# F_SERIRQ# F_LAD [0: 3] C_PCI_EC S_PLTRST O 2_SMB 1_CLK/DATA O 2_SMB 2_CLK/DATA O 2_VREF 3 VSB O 2_VDDA (O 2_3. 2 V) LPC ADC SMBUS FAN 24 M Crystal CLOCK O 2_PWM 1 (VCCSA) O 2_PWM 2 (VCCIO) O 2_PWM 3 (1. 8 SFR) PWM Refer model: P 8 Z 77 -V DELUXE EC C. SEPT 036 OP_MODE Control O 2_AD 0 (1. 05 PCH ) O 2_AD 1 (VCCIO) O 2_AD 2 (1. 8 SFR) O 2_SEN_CPUOPT O 2_AD 3 (1. 5 DUAL O 2_OP_MODE ) O 2_RSMRST# O 2_CUT_PSON# O 2_VAUX_OUT O_PWRBTN#IN_R O 2_RSTCON#_R O 2_VRMPWRGD S_SLPS 3#/S 4# O_PWROK J_SILENT#

Debug – All dots, zero, and no display Chipset (EC C. SKB 3722) Intel input voltage Output voltage Refer model: P 8 Z 77 -V LE

Debug – All dots, zero, and no display Chipset (EC C. SKB 3722) EC of S 3, S 4 signals will change with different status. Before boot up, EC will install LPC signal and sent ECPG for PWROK. After boot up, BIOS will through LPC to let EC over voltage Refer model: P 8 Z 77 -V LE

Debug – No display (PCIEX 16) 1. 2. 3. 4. 5. 6. 7. 8. Measure CPU voltage: VCORE, GFX, VCCIO, VCCSA, 1. 8 SFR, 1. 5 VDUAL Check 12 V, 3 VSB on PCIEX slot. CK_100 M_X 16 SL 1 N/P, 100 M Hz frequency from SB. O_X 16_RST#, reset signal from SIO. S_SMBCLK_SLOT has 3 V. S_SMBDATA_SLOT has 3 V. Check the TXP capacitors between PCIEX slot and CPU Check the RXP signals Others condition: P 8 some MB met PCIEX 16 has no display, Check above signals are all normal, final find VGA part signal to affect this issue.

Debug – No display (VGA) 1. FDI and DMI Bus, make sure that all LED lights are normal 2. CPU voltage: VCORE, GFX, VCCIO, VCCSA, 1. 8 SFR, 1. 5 VDUAL 3. P_GFX_OK_10, when debug code run to b 2, P_GFX_OK_10 will pull high to 3 V, at the same time, GFX power will drop from 1 V to 0. 4~0. 5 V 4. +5 V_D_VGA has 5 V 5. Check the RGB GND impedance (77 ohm) 6. Check S_VGA_VSYNC and S_VGA_HYSNC GND impedance (500 ohm) 7. Check VGA_DDC_CLK and VGA_DDC_DATA impedance (538 ohm) 8. Check PCH V_3 P 3_DAC_FB (3 V) 9. S_DAC_IREF(0. 6), after b 2 code, this signal’s power level will raise up 10. 25 M Hz crystal 11. Other device also will affect this problem EX: P 8 P 67 LE halt at b 2 Exchange USB 3. 0 IC (ASM 1042) To solve this case

ASP 1000 C • • Vcc=3. 3 V Vinsen = 0. 86 V VRHot = Vcc EN=3. 3 V • Sequence • 1. 2. 3 first • En signal • V 18 A= 1. 8 V

ASP 1000 RM • • Vcc= 5 V DVD= 1. 5 V≧ 1. 11 DVDA = 1. 33 V≧ 1. 11 EN= VCCIO≒ 1. 05 • Sequence • 1. 2. 3 first • EN signal ASP 1000 RM

ASP 1102 • Vcc 5= 5 V • Vcc 12= 12 V • EN=VCCIO≒ 1. 05 V • Sequence • 1. 2 first • EN signal ASP 1102

VCORE Driver (ASP 0 A 13) ASP 0 A 13

VCORE Driver (ASP 0 A 13) RT 9611 IR 8510

Debug - Vcore Repairing • • Vcore voltage output of each phase must have the correct waveform Empty board boot to Vcore is about 1 V boot voltage. After installing CPU, it is set with the SVID voltage, so the value is different. VCORE run normally, but still halts at 00=>check PG signals.

Debug - Driver and Component If you suspect that other components are burned, such as the Driver • To see whether the appearance of any abnormalities. • Impedance measure: Measuring the ESD diodes, the terminal is connected to GND. • To remove the component measurement is abnormal compared to the impedance and normal components of each pin to ground. • If Vcore is short circuit and +3. 3 V is short circuit, SIO may have burned.

Debug – 5 VSB 1. Clear COMS and let MB at load default status 2. Check +5 VSB_ATX 3. Check O_DEEPS 5 and PQ 305 high low

Debug – 3 VSB_ADV & 3 VSB 1. 2. 3. 4. 5. 0 ohm 3 VSB 5 VSB P_3 VSB_VDD_10 P_3 VSB_PVDD_S P_+3 VSB_RT_10 P_3 VSB_R_FB_10

Debug – 5 VDUAL 1. Check O_3 VSBSW# (At S 0 and S 5 status, this signal has 3 V) 2. Check PQ 601 PIN 1(12 V) and PIN 3(5 V) low low high

Debug – 1. 5 VDUAL and PU 501 VCC 2. Check P_1 V 5 DUAL_OCSET/EN_10 3. Check MOS The impedance is 25 K 6. Check P_1 V 5 DUAL_FB_10 has 0. 8 V 7. Check NCT 3933 working condition (VCC, S_SMBDATA_VSB, S_SMBCLK_VSB)

Debug – VCCIO 8. 2 K ohm 25. 5 K ohm Low

Debug – 1. 8 SFR & VCCSA 4. 7 K ohm 3 VSB 10 K 26. 1 K P_1 V 8_SFR_IN+_10 P_VCCSA_IN+_10 11. 5 K 10 K

Q&A Thank You!