2005 Mil/Aerospace Applications of Programmable Logic Devices International Conference (MAPLD) National Aeronautics and Space Administration Multi-level Simulation of a Real Time Vibration Monitoring System Component Bryan Robertson/EI 31 NASA/Marshall Space Flight Center Robertson Page MAPLD 2005/157
2005 Mil/Aerospace Applications of Programmable Logic Devices International Conference (MAPLD) National Aeronautics and Space Administration ØHealth Management System Overview ØRTVMS Design Overview ØSimulation Environment ØSimulation Details ØSummary Robertson Page 2 MAPLD 2005/157
2005 Mil/Aerospace Applications of Programmable Logic Devices International Conference (MAPLD) National Aeronautics and Space Administration Health Management System Overview Ø A Real-Time Vibration Monitoring System (RTVMS) was developed by MSFC and currently operates at the Stennis Space Center (SSC) during Space Shuttle Main Engine (SSME) test firings. Ø The RTVMS provides real-time vibration analysis and health monitoring capabilities during engine operation by producing vibration spectral data from critical SSME Components. This vibration analysis provides the capability to activate a vibration flight redline for engine high pressure turbomachinery. Ø For the RTVMS time resolution is critical. Parallel processing and multiple DSPs are required to perform the FFTs and health algorithms required. Ø In early 2000 the MSFC Shuttle Main Engine Project Office decided to pursue implementation of the RTVMS technology for Space Shuttle Flights. This advanced flight RTVMS would contain all the features of the current SSC ground RTVMS system but would also include additional algorithms that would also evaluate the vibration data in the phase domain. Ø The fist step toward implementing the flight RTVMS systems was to develop a ‘flight-like’ health management system that incorporated the RTVMS and other existing engine monitoring systems. This system is called the Health Management Computer – Integrated Rack Assembly (HMC-IRA). The RTVMS design for the HMC-IRA will be covered in this presentation. Robertson Page 3 MAPLD 2005/157
2005 Mil/Aerospace Applications of Programmable Logic Devices International Conference (MAPLD) National Aeronautics and Space Administration Health Management Computer – Integrated Rack Assembly (HMC-IRA) • Ground based system – designed as ‘flight-like’ while maintaining low cost. – Simulates an Advanced Health Management System (AHMS) Shuttle Main Engine Controller flight system processing environment. – Provides a Real Time Vibration Monitoring System (RTVMS) design that can transition to a flight system design with only form-fit modifications. – Provides flexibility for growth and alternate software configurations and hardware additions. • Provide interfaces for: – AHMS Space Shuttle Main Engine Controller (SSMEC) AHMS(Phase 1) SSME Block II – Space Shuttle Main Engine (SSME) sensors Controller – Stennis Space Center (SSC) Data Acquisition System. • Development of three Brassboard HMC-IRA and three Special Test Equipment Units – Planned operation with a SSMEC during SSME Hot-fires at SSC – Supports SSMEC operations at the MSFC SSMEC Hardware Simulation Lab – Supports software development at the Rocketdyne Controller Simulation Lab. • System Development and Verification is complete on all units and are currently waiting for Integration into the SSC facility. Robertson Page 4 MAPLD 2005/157
2005 Mil/Aerospace Applications of Programmable Logic Devices International Conference (MAPLD) National Aeronautics and Space Administration Radstone EP 1 A-8240 Radstone EPMCQ 2 R PMC SEAKR Nv. M Robertson • The HMC-IRA consists of custom and COTS components. – Three Power. PC 603 processors – Ten TMS 320 C 40 DSPs on two RTVMS boards. • All DSPs interconnected through serial ports. On-board and board-board. • All 10 DSPs receive the sensor data from the two analog cards simultaneously. • DSPs can be configured in a variety of parallel processing configurations. • All DSPs have access to the main VME bus. – 1. 5 Gbyte Non-volatile Memory board – Two Analog cards • SSMEC, SSME, and SSC interfaces • Dual sampling rates • VME and DSP serial interfaces. – Three SSMEC RS 485 High Speed Serial Interfaces – Customized VME backplane supporting serial communication channels between RTVMS and analog boards. Page 5 RTVMS Basecard and mezzanine MAPLD 2005/157
2005 Mil/Aerospace Applications of Programmable Logic Devices International Conference (MAPLD) National Aeronautics and Space Administration Robertson Page 6 MAPLD 2005/157
2005 Mil/Aerospace Applications of Programmable Logic Devices International Conference (MAPLD) National Aeronautics and Space Administration Real Time Vibration Monitoring System (RTVMS) Overview • • First EI 31 Multiple/Parallel Processing Digital Signal Processor (DSP) Design. First design to use System level simulations Design was required to have a path to flight. – Designed with commercial version of flight quality components. – EEE Parts evaluation performed on selected flight components Challenging Printed Circuit Board Design – First 16 layer board. Previous ED 16 designed board had max 14 layers. – Most densely populated board routed by ED 16. 1012 components for baseboard, greater than 1800 total. 1. 5 to 2 times more components than any previous ED 16 design. – 28 mil Via sizes utilized for the first time (previous size was 40 mil – Developed PCB procurement standards now being used by other projects Robertson Page 7 MAPLD 2005/157
2005 Mil/Aerospace Applications of Programmable Logic Devices International Conference (MAPLD) National Aeronautics and Space Administration Real Time Vibration Monitoring System (RTVMS) Design Ø A 32/D 32 VME Master w/ Block and RMW transfer capability Ø A 24/D 32 VME Slave 8 K x 32 Dual-Port SRAM Ø 5 Texas Instruments 320 C 40 HFHM 50 DSPs (4 for algorithm processing and 1 for communications) Ø 512 K x 32 (2 Mbytes) of SRAM on Local Bus of each DSP Ø 512 K x 32 (2 Mbytes) of SRAM on Global Bus of each DSP Ø 32 K x 32 of EEPROM on Global Bus of each DSP for boot operations Ø 8 k x 32 Dual-Port SRAM on Global Bus that is shared between the DSPs Ø Communications Port Interface with EADIFA and EADIFB boards Ø Communications Port Interface between the DSPs Ø 2 Actel A 54 SX 32 A FPGAs for various logic applications Robertson Page 8 MAPLD 2005/157
2005 Mil/Aerospace Applications of Programmable Logic Devices International Conference (MAPLD) National Aeronautics and Space Administration Elements of Simulation Environment – VHDL Behavioral (Functional) Simulation CASE addr IS WHEN "01000" => flash <= '0'; WHEN "01001" => flash <= '1'; WHEN "01010" => mps_pwr <= '1'; WHEN "01011" => mps_pwr <= '0'; WHEN "01100" => eng_pwr <= '1'; WHEN "01101" => eng_pwr <= '0'; WHEN "01110" => x_tvc_en <= '0'; WHEN "01111" => x_tvc_en <= '1'; VHDL logic implemented in 2 Actel A 54 SX 32 A FPGAs Synthesize & Target (Actel, Xilinx, Altera, etc. ) Timing Simulation Place & Route (Structural VHDL) Robertson Page 9 MAPLD 2005/157
2005 Mil/Aerospace Applications of Programmable Logic Devices International Conference (MAPLD) National Aeronautics and Space Administration Elements of Simulation Environment – Synopsys Software Models • Licensed models of components or protocols such as memories, logic circuits, VME communication, etc. - Used to verify interfacing properties such as setup and hold timing, bus contention, etc. - Have some adjustable parameters to optimize for application • Not suitable for complex circuits such as DSPs if high-fidelity simulations required VHDL Software Model Representation entity and_gate is port ( x, y : in std_logic; z : out std_logic ); begin end and_gate; Gate Level Component x z y architecture a 1 of rtvms_int_blk is begin z <= x and end; Robertson Page y; MAPLD 2005/157
2005 Mil/Aerospace Applications of Programmable Logic Devices International Conference (MAPLD) National Aeronautics and Space Administration Elements of Simulation Environment – Synopsys Hardware Model • Built by Synopsys using actual chips and interfaced to Hardware Modeler - Actual silicon communicates with simulators - Much faster than software models - Elementary software code can be executed on microprocessors • Design and Simulation Tools reside on individual office computers Hardware Model Operation in B 222 Lab TMS 320 C 40 DSP MSFC Network Designer’s Office PC Interface to Hardware Models XPLORER MS-3 X 00 Designer’s Office HDL Simulator Model. Source XPLORER MS-3 X 00 Model. Source Fiber Optic Link Robertson Ethernet Link Page 11 Designer’s Office MAPLD 2005/157
2005 Mil/Aerospace Applications of Programmable Logic Devices International Conference (MAPLD) National Aeronautics and Space Administration Mentor Graphics Design Capture Environment • Where the Elements of Design are “connected” together CASE addr IS WHEN "01000" => flash <= '0'; WHEN "01001" => flash <= '1'; WHEN "01010" => mps_pwr <= '1'; WHEN "01011" => mps_pwr <= '0'; WHEN "01100" => eng_pwr <= '1'; WHEN "01101" => eng_pwr <= '0'; WHEN "01110" => x_tvc_en <= '0'; WHEN "01111" => x_tvc_en <= '1'; Hardware Modeler Symbols HDL Over 14, 000 Fully Functional Models -- Memories -- Standard MSI/LSI Logic -- Bus functional microprocessors/DSP -- Bus functional microcontrollers -- Bus Interfaces (VME, PCI) -- Memories can be loaded with software to allow full board level simulation Robertson Page 12 Software Model Library Symbols MAPLD 2005/157
2005 Mil/Aerospace Applications of Programmable Logic Devices International Conference (MAPLD) National Aeronautics and Space Administration Model. Simulation Environment VHDL Simulation Hardware Modelers Schematic Capture HDL Over 14, 000 Fully Functional Models -- Memories -- Standard MSI/LSI Logic -- Bus functional microprocessors/DSP -- Bus functional microcontrollers -- Bus Interfaces (VME, PCI) -- Memories can be loaded with software to allow full board level simulation CASE addr IS WHEN "01000" => flash <= '0'; WHEN "01001" => flash <= '1'; WHEN "01010" => mps_pwr <= '1'; WHEN "01011" => mps_pwr <= '0'; WHEN "01100" => eng_pwr <= '1'; WHEN "01101" => eng_pwr <= '0'; WHEN "01110" => x_tvc_en <= '0'; WHEN "01111" => x_tvc_en <= '1'; Software Model Library Robertson Page 13 MAPLD 2005/157
2005 Mil/Aerospace Applications of Programmable Logic Devices International Conference (MAPLD) National Aeronautics and Space Administration RTVMS Design Flow Synopsys Software Models Symbols Synopsys Hardware Models Symbols Synplicity/Leonardo Synthesis Tools Functional Or Synthesized VHDL Code Mentor Schematic Entry Re-Synthesize Compile Design Mentor Design Capture FPGA Libraries Hardware/Software Libraries Synopsys Robertson Modify VHDL Code If Necessary Generate VHDL Netlist Compile for Simulation Run Simulations Verify Design Parameters Mentor Simulator Page 14 MAPLD 2005/157
2005 Mil/Aerospace Applications of Programmable Logic Devices International Conference (MAPLD) National Aeronautics and Space Administration Simulation Test Code Details Ø C test code was executed on the TMS 320 C 40 Hardware Model(not real time) Ø Each TI DSP contained four 32 K x 8 EEPROMs for boot operations Ø The code was written and compiled utilizing TI’s C 40 Code Composer Ø The compiled code was partitioned into 4 sections utilizing the hex 30 command hex 30 EEPROM. out -i -romwidth 8 -memwidth 32 -o EEPROM. lo 1 -o EEPROM. lo 2 -o EEPROM. hi 1 -o EEPROM. hi 2 Ø Each 8 -bit EEPROM file was then converted to Intel hex format utilizing a custom conversion program(Intel_Hex_MIF_Conv. exe) Ø Each EEPROM Synopsys software model instance in the Mentor Graphics Design Capture tool contained a memory file attribute that linked the model with a corresponding EEPROM file Ø At boot in the Model. Sim environment, each DSP Hardware Model instance would execute the code located in its corresponding EEPROM files Robertson Page 15 MAPLD 2005/157
2005 Mil/Aerospace Applications of Programmable Logic Devices International Conference (MAPLD) National Aeronautics and Space Administration RTVMS Component Level Verification Ø Functional Simulations were initially utilized to verify the Hardware Model and its surrounding logic. The simulations included. . • Ability to boot correctly from EEPROMs • 512 k x 32 SRAM Access(Global and Local) Ø The timing of the simulation could be manipulated the following two ways: • TMS 320 C 40 Hardware Model timing attribute • Synopsys Logic Memory Models timing attribute Ø Various simulations were run where the timing attributes were modified to simulate multiple conditions. Robertson Page 16 MAPLD 2005/157
2005 Mil/Aerospace Applications of Programmable Logic Devices International Conference (MAPLD) National Aeronautics and Space Administration RTVMS Board Level and FPGA Verification Ø Once the Hardware Model and its surrounding logic were verified, the simulations were expanded to include RTVMS Board and FPGA verification. The simulations included. . • MGBC FPGA Register Access • MGBC FPGA Watchdog Operation • Dual-Port SRAM Access with arbitration inside the MGBC FPGA • DSP to DSP Comport Operations Ø Once the functionality was verified, the FPGA code was synthesized and the simulations repeated multiple times. The timing of the simulation could be manipulated in three ways in the: • TMS 320 C 40 Hardware Model timing attribute • Synopsys Logic Memory Models timing attribute • Synthesized FPGA logic delays (min, typ, max) Robertson Page 17 MAPLD 2005/157
2005 Mil/Aerospace Applications of Programmable Logic Devices International Conference (MAPLD) National Aeronautics and Space Administration HMC-IRA System Level Verification Ø The system level verification consisted of the following components to simulate multiple boards in a VME chassis: • 2 RTVMS Board Designs(Master and Slave) • 1 EADIF-A Board Design(Slave) • 1 VME Hardware Verification Logic Model(Master, Slave, System Controller) Ø PCL code was written for the VME Hardware Verification Model to operate as a System Controller Ø Functional and Timing simulations were executed to verify the following: • RTVMS VME Accesses(Single, Block, and Read-Modify-Write) of the System Controller • Execution of VME Interrupts • On-board VME Arbitration • VME Access of the RTMVS DPSR by the System Controller(RTVMS as a Slave) • EADIF-A to RTVMS DSP Comport Operation Robertson Page 18 MAPLD 2005/157
2005 Mil/Aerospace Applications of Programmable Logic Devices International Conference (MAPLD) National Aeronautics and Space Administration Advantages of Board and System Level Simulations Ø Box and Board Level Simulations Provide a Unique Capability Ø More Complex Design Capability Ø Lower Cost – Fewer Design Iterations and Reduced Debug Time Ø Higher Reliability due to Timing Analysis Capability Ø The potential to substantially decrease development time over traditional methods Ø Test code used as a foundation for the development of system software that can occur in parallel to hardware development. Robertson Page 19 MAPLD 2005/157
2005 Mil/Aerospace Applications of Programmable Logic Devices International Conference (MAPLD) National Aeronautics and Space Administration Disadvantages of Board and System Level Simulations Ø Simulation != Analysis Ø Simulations are limited to small time segments Ø Simulation tools are expensive Ø Upfront design time increased (Longer time to initial product) Robertson Page 20 MAPLD 2005/157
2005 Mil/Aerospace Applications of Programmable Logic Devices International Conference (MAPLD) National Aeronautics and Space Administration Summary Ø Ø Ø The HMC-IRA RTVMS boards have completed all board level and system level verification tests and are waiting for delivery to the Stennis Space Center. During testing no design errors with the 15 Engineering Unit and Brassboard were encountered. Only slight modifications to the design was made between the Engineering Unit and Brassboard Unit boards. These changes were for routing purposes. The Engineering Unit boards met all requirements , re-spin of board would not have been required Because of the detailed simulations and schedule time allocated for performing the simulations, no functional or timing errors have occurred. Only one printed circuit board assembly had a manufacturing issue. Only one significant component failure with a SRAM. Robertson Page 21 MAPLD 2005/157
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