ﺍﻟگﻮﺭﻳﺘﻤﻬﺎﻱ ﻃﺮﺍﺣﻲ ﻓﻴﺰﻳﻜﻲ VLSI 1

ﻣﺮﺍﺟﻊ • • • 1. 2. Andrew B. Kahng, Jens Lienig, Igor L. Markov and Jin Hu, VLSI Physical Design: From Graph Partitioning to Timing Closure, Springer, 2011. N. Sherwani, “Algorithms for VLSI Physical Design Automation”, 3 rd edition, Kluwer Academic Publishers, Boston, MA, 1999. T. H. Cormen, C. E. Leiserson and R. L. Rivest, “Introduction to Algorithms”, Mc. Graw-Hill, New York, NY, 1990. Practical Problems in VLSI Physical Design Automation, Sung Kyu Lim, Springer, 2008. P. Lee, “Introduction to Place and Route Design in VLSI, ” Lulu, 2007. Charles J. Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar, Handbook of Algorithms for Physical Design Automation, ed. , Taylor & Francis Group, 2009. L. Scheffer, L. Lavagno, G. Martin, “EDA Handbook (EDA for IC Implementation, Circuit Design, and Process Technology), ”, Ed. , CRC Press, 2006. 2

VLSI CAD Conferences • DAC Ø Design Automation Conference • ICCAD Ø Int’l Conference on Computer-Aided Design • ISPD Ø Int’l Symposium of Physical Design • ASP-DAC Ø Asia and South Pacific DAC 3

VLSI CAD Conferences • DATE (EDAC) Ø Design Automation and Test in Europe • ISCAS Ø Int’l Symposium on Circuits and Systems • ICCD Ø Int’l Conference on Computer Design • APC-CAS Ø Asia-Pacific Conference on Circuits and Systems 4

VLSI CAD Journals • IEEE TCAD Ø IEEE Transactions on CAD • ACM TODAES Ø ACM Transactions on Design Automation of Electronic Systems • Integration, the VLSI Journal • IEEE Transactions on Circuits and Systems • IEEE Transactions on VLSI Systems • IEEE Transactions on Computers 5

Web Sites • Papers: http: //scholar. google. com/ • Benchmarks: http: //vlsicad. eecs. umich. edu/BK/Slots/slots/Circ uitand. Microprocessor. Design. Examples. html http: //vlsicad. eecs. umich. edu/BK/Slots/slots/Wir elengthdriven. Standard. Cell. Placement. html http: //www. cbl. ncsu. edu/benchmarks/ 6

Web Sites • VLSI CAD Bookshelf: http: //vlsicad. eecs. umich. edu/BK/ • VLSI Design Automation Café: http: //www. edacafe. com 7

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Integrated Circuits (ICs) • What are they? Ø Electrical components built by layering different materials on a silicon base (wafer) • IC Designer Ø Transforms a circuit description into a geometric description - Layout process 11

Integrated Circuits B 12

Size Issue 50 -70 microns 0. 025 microns Tens of 13

Moore’s Law In 1965, Gordon Moore: • Number of transistors on an IC doubles every year. • 10 years later, he revised it: doubles every 18 months 14

VLSI Physical Design Automation • Modern chip design: very complex • Largely performed by specialized software ØTools are frequently updated to reflect − improvements in semiconductor technologies − increasing design complexities 15

VLSI Physical Design Automation • User of this software needs: Øa high-level understanding of the implemented algorithms. • Developer of this software needs an understanding of : Øhow various algorithms operate and interact Øwhat their performance bottlenecks are 16

Questions Ø How is functionally correct layout produced from a netlist? (Analysis) netlist physical design layout Ø How do we develop and improve software for VLSI physical design? (Algorithm design) 17

System Specification ENTITY test is port a: in bit; end ENTITY test; Architectural Design Functional Design and Logic Design Circuit Design Physical Design DRC LVS ERC Physical Verification and Signoff Fabrication Packaging and Testing Chip 19

System Specification • Specify overall goals and high-level requirements: Ø Functionality Ø Performance Ø Physical dimensions Ø Production technology Ø Overall power constraints • Trade-offs: Ø Market requirements, costs, economical viability 20

Architectural Design • Define basic architecture to meet the system specifications: Ø Integration of analog and mixed-signal blocks Ø Memory management (serial/parallel? ) + addressing scheme Ø Number and types of computational cores − E. g. , processors and DSP algorithms/units Ø Internal and external communication − support for standard protocols, … 21

Architectural Design (cont’d) • Define basic architecture to meet the system specifications: Ø Hard/soft IP blocks Ø Pinout, packaging and die-package interface Ø Power requirements Ø Choice of process technology and layer stacks 22

Functional and Logic Design • Functional design: Ø Main functional units and their interconnections Ø Behavioral specification of each module (not implementation) − input-output mapping − timing behavior 23

Functional and Logic Design • Logic design: Ø RTL spec. in VHDL/Verilog + target library Ø Logic synthesis and simulation Ø Result: Netlist i. t. o. library elements 24

Netlist (a : N ) 1 (b : N ) Pin-Oriented Netlist 2 (c : N ) 5 (x: IN 1 N , IN 2 N , OUT N ) 1 2 3 (y: IN 1 N , IN 2 N , OUT N ) 1 2 4 (z: IN 1 N , IN 2 N , OUT N ) 3 4 5 (N : a, x. IN 1, y. IN 1) 1 (N : b, x. IN 2, y. IN 2) 2 (N : x. OUT, z. IN 1) 3 (N : y. OUT, z. IN 2) 4 (N : z. OUT, c) 5 Net-Oriented Netlist 25

RTL Specification • RTL: ØControl flow ØRegister allocation ØData path: −Arithmetic operations −Logic operations −Buses and interconnections 26

Circuit Design • Some critical modules must be designed at the transistor level: ØSRAM blocks ØI/O ØAnalog circuits ØHigh-speed functions ØElectro-static discharge (ESD) protection circuits • Verification by SPICE simulation 27

Physical Design Circuit Description Geometrical Description Manufacturing 28

System Specification ENTITY test is port a: in bit; end ENTITY test; Architectural Design Functional Design and Logic Design Circuit Design Physical Design DRC LVS ERC Physical Verification and Signoff Partitioning Chip Planning Placement Clock Tree Synthesis Signal Routing Fabrication Packaging and Testing Timing Closure Chip 29

• DRC: Physical Verification Ø Checks technology-imposed constraints • Circuit extraction and LVS: Ø Layout netlist Ø Compare with original netlist • Parasitic extraction: Ø Layout RC(L) circuit Ø Check for electrical characteristics • Antenna rule checking: Ø Antenna effects damage transistors • ERC: Ø power and ground connections Ø signal transition time (slew) Ø fan-out constraints 30

Fabrication • Tapeout (Stream out): Ø Generation of layout data in GDSII format Ø Delivering the design to manufacturing process • Wafer size: 200 -300 mm • Die size: 25 mm 2 − Layout is converted to several dozens of photolithographic masks 31

Testing and Packaging 32

Physical Design • Arrange devices on a plane • Determine interconnection paths so that ØConstraints: − Functionality is preserved − Performance constraints are met − Manufacturing design rules are met ØMetrics for optimization: − …. 33

Physical Design • Metrics: Ø Performance: − Gate delays and interconnect delays Ø Area: − larger chips higher costs + slower chips + higher power Ø Reliability: − E. g. vias Ø Power consumption Ø Yield • Efficiency of algorithms 34

Physical Design Cycle Partitioning Placement/ Floorplanning Routing Break the circuit up into smaller segments Place the segments on the chip Lay out the wire paths 35

System Specification ENTITY test is port a: in bit; end ENTITY test; Architectural Design Functional Design and Logic Design Circuit Design Physical Design DRC LVS ERC Physical Verification and Signoff Partitioning Chip Planning Placement Clock Tree Synthesis Signal Routing Fabrication Packaging and Testing Timing Closure Chip 36

(Partitioning) ﺍﻓﺮﺍﺯ • Reasons: • Highly complex circuits • Memory limitation of computers • Speed limitation of computers Sets of partitions Netlist Number of partitions Block sizes Partitioner Partitions netlist 37

(Partitioning) ﺍﻓﺮﺍﺯ 38

Chip Planning • Floorplanning: Ø Determines shapes and arrangements of modules Ø Frequently done manually • Power & ground routing: Ø Distributes VDD and GND nets throughout the chip • Pin assignment: Ø Determines the locations of ports 39

(Floorplanning) ﺟﺎﺳﺎﺯﻱ Recently, So. Cs with many cores: Manual floorplanning not possible Deadspace 40

(Placement) ﺟﺎﻳﺎﺑﻲ 41

Clock Network Synthesis • Determines: Ørouting of the clock signal Øbuffering Øclock gating (e. g. , for power management) • Constraints to meet Øprescribed skew Ødelay requirements Ø(power requirement) 42

Clock Network Synthesis 43

(Signal Routing) ﻣﺴﻴﺮﻳﺎﺑﻲ • Complete interconnections between blocks Ø acc. to netlist • Routing area: Ø Channels Ø Switchboxes • Global routing: Ø Specifies which channels/switchboxes are to be used for each net • Detailed routing: Ø Specifies exact interconnections within various ch/sb 44

Global Routing Cell 1 Cell 2 45

Detailed Routing Ø The actual wires are routed in the channel Ø The goal of the entire process: − To produce the shortest wires and consume the least amount of space Cell 1 Cell 2 46

Timing Closure • Optimizes circuit performance by specialized placement and routing techniques Ø RC(L) Extraction: − Layout circuit Ø Timing Analysis: − Calculate delays and determine critical path(s) Ø Timing Optimization 47

History Time Period Circuit and Physical Design Process Advancements 1950 -1965 Manual design only. 1965 -1975 Layout editors, e. g. , place and route tools, first developed for printed circuit boards. 1975 -1985 More advanced tools for ICs and PCBs, with more sophisticated algorithms. 1985 -1990 First performance-driven tools and parallel optimization algorithms for layout; better understanding of underlying theory (graph theory, solution complexity, etc. ). 1990 -2000 First over-the-cell routing, first 3 D and multilayer placement and routing techniques developed. Automated circuit synthesis and routability-oriented design become dominant. Start of parallelizing workloads. Emergence of physical synthesis. Design for Manufacturability (DFM), optical proximity correction (OPC), and other techniques emerge at the designmanufacturing interface. Increased reusability of blocks, including intellectual property (IP) blocks. 2000 - now Deeper level of integration (instead of indep’t point tools) 48