Скачать презентацию TAB GAB Production Readiness Review Hal Evans Скачать презентацию TAB GAB Production Readiness Review Hal Evans

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TAB & GAB Production Readiness Review Hal Evans for the Nevis Group In a TAB & GAB Production Readiness Review Hal Evans for the Nevis Group In a Nutshell u u We have the components, the boards, the money… Should we assemble the TABs and GABs? Concentrate on u Hardware Design & Testing Production Readiness Less Emphasis u H. Evans Project Justification, Algorithm Devel, Install/Commission TAB/GAB PRR: 7 -Oct-04 1

The Nevis Team Students Chad Johnson, Jovan Mitrevski Postdocs Sabine Lammers, TBA Engineers Jaro The Nevis Team Students Chad Johnson, Jovan Mitrevski Postdocs Sabine Lammers, TBA Engineers Jaro Ban, Bill Sippach + Nevis Tech’s Faculty Hal Evans, John Parsons H. Evans TAB/GAB PRR: 7 -Oct-04 2

The Tevatron Landscape Accelerator Plan: FY 05 -09 2. 8 e 32 ! install The Tevatron Landscape Accelerator Plan: FY 05 -09 2. 8 e 32 ! install upgrades current peak L H. Evans TAB/GAB PRR: 7 -Oct-04 3

Trigger Challenges Trigger Run IIa Definition Example Channel L 1 Rate [k. Hz] (no Trigger Challenges Trigger Run IIa Definition Example Channel L 1 Rate [k. Hz] (no upgrade) L 1 Rate [k. Hz] (w/ upgrade) EM 1 EM TT > 10 Ge. V W ev WH evjj 1. 3 0. 7 Di. EM 1 EM TT > 7 Ge. V 2 EM TT > 5 Ge. V Z ee ZH eejj 0. 5 0. 1 Muon 1 Mu Pt > 11 Ge. V CFT Track W v WH vjj 6 1. 1 Di-Mu 2 Mu Pt > 3 Ge. V CFT Tracks Z/ ZH jj 0. 4 <0. 1 e + Jets 1 EM TT > 7 Ge. V 2 Had TT > 5 Ge. V WH evjj tt ev+jets 0. 8 0. 2 Mu + Jet 1 Mu Pt > 3 Ge. V 1 Had TT > 5 Ge. V WH vjj tt v+jets <0. 1 Jet+MEt 2 TT > 5 Ge. V MEt > 10 Ge. V ZH vvbb 2. 1 0. 8 Mu+EM 1 Mu Pt > 3 Ge. V + Trk 1 EM TT > 5 Ge. V H WW, ZZ <0. 1 Iso Trk Pt > 10 Ge. V H , W v 17 1. 0 Di-Trk 1 Iso Trk Pt > 10 Ge. V 2 Trk Pt > 5 Ge. V 1 Trk matched w/ EM H 0. 6 <0. 1 Total Rate H. Evans ~30 TAB/GAB PRR: 7 -Oct-04 3. 9 Luminosity 2 1032 BC 396 ns L 1 Limit ~3 k. Hz 4

Meeting the Challenge Detector Level 1 2. 5 Mhz Level 2 3 khz Detector Meeting the Challenge Detector Level 1 2. 5 Mhz Level 2 3 khz Detector 1 khz Level 1 2. 5 Mhz CAL L 1 Cal L 2 Cal c/f PS L 1 PS L 2 PS CFT L 1 CTT L 2 CTT c/f PS L 2 STT CFT L 2 Mu 3 khz SMT MU FPD Lumi L 1 Mu Run IIa H. Evans Global L 2 Level 3 L 1 Cal L 2 Cal Cal. Trk MU L 1 FPD Framework CAL Level 2 FPD Lumi TAB/GAB PRR: 7 -Oct-04 L 1 PS L 1 CTT L 2 PS L 2 CTT L 2 STT L 1 Mu L 2 Mu L 1 FPD Framework Run IIb Global L 2 Level 35

L 1 Cal Overview Cables: UIC Cal-Track Match: Arizona Find EM LMs Digitize Filter L 1 Cal Overview Cables: UIC Cal-Track Match: Arizona Find EM LMs Digitize Filter + E Et Build EM Find EM+H LMs Build JETs ADF: Saclay, MSU Et, Ex, Ey Sums H. Evans TAB: Nevis TAB/GAB PRR: 7 -Oct-04 Build TAUs Construct And/Or’s GAB: Nevis 6

Board Rundown : In / Out Custom Board No Purpose ADF: ACD/Dig. Filt. 80 Board Rundown : In / Out Custom Board No Purpose ADF: ACD/Dig. Filt. 80 digitize, filter, E-to-Et SCLD: ADF Timing F’out 4 ADF control/timing TAB: Trig Algo Board 8 algo’s, Cal-Trk out, sums GAB: Global Algo Board 1 sums, trigs to FWK all VME/SCL Board 1 VME & timing to TAB/GAB all Splitter 4 Collect data in parallel w/ IIa System 4 TTs (8 chan’s) Match BLS cables to ADF inputs w/out rerunning 8 4 / 2 4 4 BLS-ADF Cables & Patch Panels, etc. H. Evans TAB/GAB PRR: 7 -Oct-04 4 4 / 4 4 all 40 9 / 31 4 7

Algorithm Flow Find Local Maxima Make Regions of Interest TT Input (corrected w/ ICR) Algorithm Flow Find Local Maxima Make Regions of Interest TT Input (corrected w/ ICR) Construct Objects Compare to Thresholds 5 5 5 1 5 5 TT Space H. Evans 5 5 6 f 5 5 5 1 1 1 5 ROI Space h LM Space TAB/GAB PRR: 7 -Oct-04 Jet Space 8

Objects Object Outputs Cuts during Construction Thresholds (i = 1 -7) EM ET EM(2 Objects Object Outputs Cuts during Construction Thresholds (i = 1 -7) EM ET EM(2 x 2) · HD(4 x 4) < EM(2 x 2) / 23 · EM(ring) < cut (adc cnts) ET > EM Thr-i Jet ET EM+HD(4 x 4) · none ET > Jet Thr-i Tau ET EM+HD(2 x 2) R = EM+HD(2 x 2) / (4 x 4) · [(2 x 2) x (1/4 x 4)LUT 8 -bit] 8 -bit =R ET & R vs Thr (t. b. d. ) Sums S EM+HD(4 x 1) for = 2, 3, 4, 5 · currently none · (TT > thr, | | < cut, …) none EM Algo H. Evans Jet Algo TAB/GAB PRR: 7 -Oct-04 Tau Algo 9

Algo’s vs Architecture TAB 7 =31 -28 TAB 6 =27 -24 TAB 5 TAB Algo’s vs Architecture TAB 7 =31 -28 TAB 6 =27 -24 TAB 5 TAB 4 =23 -20 =19 -16 TAB 3 TAB 2 =15 -12 TAB 1 =11 -8 =7 -4 TAB 0 =3 -0 10 =39 -0 =31 -28 ADFs 79 -70 1. =39 -0 =27 -24 ADFs 69 -60 =39 -0 =23 -20 ADFs 5950 =39 -0 =19 -16 ADFs 49 -40 ADFs 29 -20 ADFs 19 -10 =39 -0 =3 -0 ADFs 9 -0 SW Chip input 9 x 9 SW Chip output 4 x 4 Algo TTs for 1 LM LMs / SW 2, 0, 1 4 x 4 6 x 6 2, 1, 1 6 x 6 4 x 4 2, 2, 1 8 x 8 2 x 2 3, -1, 1 5 x 5 3, 0, 1 TAB/GAB PRR: 7 -Oct-04 7 x 7 3 x 3 Minimize Data Sharing 3 Identical outputs from each ADF (4 x 4 x 2 TTs) Each TAB: 40 x 9 inputs & 31 x 4 outputs H. Evans ADFs 39 -30 =39 -0 =7 -4 10 3. Construct Local Maxima Use ICR in Jets + Data to Cal-Track All eta to each TAB 2. =39 -0 =11 -8 =39 -0 =15 -12 10 10

VME/SCL Board · New Comp. of TAB/GAB system u u · proposed: change control: VME/SCL Board · New Comp. of TAB/GAB system u u · proposed: change control: VME (custom protocol) s u u not enough space on TAB for standard VME D 0 Trigger Timing (SCL) (previously part of GAB) Why Split off from GAB u u · VME interface Interfaces to u · Feb 03 Mar 03 local osc’s & f’out (standalone runs) simplifies system design & maintenance allows speedy testing of prototype TAB Fully Tested: Jun 03 serial out x 9 (VME & SCL) H. Evans TAB/GAB PRR: 7 -Oct-04 SCL interface DONE 11

TAB Channel Link Receivers (x 30) DC/DC conv power VME/SCL ADF Inputs (x 30) TAB Channel Link Receivers (x 30) DC/DC conv power VME/SCL ADF Inputs (x 30) thru custom b’plane L 2/L 3 Output (optical) Output to GAB Global Chip Output to Cal-Track (x 3) H. Evans Sliding Windows Chips (x 10) TAB/GAB PRR: 7 -Oct-04 12

GAB power VME/SCL L 2/L 3 out to TFW TAB Inputs (x 8) H. GAB power VME/SCL L 2/L 3 out to TFW TAB Inputs (x 8) H. Evans TAB/GAB PRR: 7 -Oct-04 13

Data-Eye View of L 1 Cal L 2 Cal & L 3 180 16 Data-Eye View of L 1 Cal L 2 Cal & L 3 180 16 b ADF S. W. 9 Rcv 3 x 10 x 30 x 80 S. W. 0 ADF 36 8 b + 6 8 b sp. TAB all data xmit & math operations done bit-serially @ 90 MHz H. Evans Global 10 ? ? ? 1 6 b 49 12 b + 3 12 b sp. 21 12 b + 4 12 b sp. 5 16 b sp. + 2 16 b 5 16 b + 2 16 b sp. Cal. Trk TAB/GAB PRR: 7 -Oct-04 x 8 And/Or Rcv 0 64 b GAB + 16 b sp. Cal. Trk 14

TAB to GAB Data Path Intra-TAB: SW Global · Clusters 12 lines u u TAB to GAB Data Path Intra-TAB: SW Global · Clusters 12 lines u u 16 -EM + 16 -H+ 16 -TAU each clust = 3 -bits (highest of 7 thr’s pass) TAB to GAB: Global Rcv · EM Counts 12 words · H Counts 12 words · TAU Counts 12 words u · Sum(EM+H Et) u u sum over for each · Data for L 2/L 3 u 4 lines 6 thr’s – 2 bit counts S, C, N regions 2 lines on L 1 Accept · Stat/BX/Frame · Spare 4 lines 3 lines · Sum(EM+H) 3 words u Et, Ex, Ey · Stat/Ctrl/… 7 words · Spare 3 words All Formats: www. nevis. columbia. edu/~evans/l 1 cal/hardware/tab_gab_comm. html H. Evans TAB/GAB PRR: 7 -Oct-04 15

Data Transmission Link Method Clock ADF to TAB LVDS – Channel Link xmit/rcvr 424 Data Transmission Link Method Clock ADF to TAB LVDS – Channel Link xmit/rcvr 424 MHz TAB to GAB LVDS – Stratix xmit/rcvr 636 MHz TAB to Cal-Track Gbit Cu Coax – Arizona SLDB xmit/rcvr 950 MHz TAB/GAB to L 2/L 3 G-Link Optical xmit Optical split for L 2/L 3 branch GAB to TFW ECL Ribbon Cable SCL to TAB/GAB Simple Serial Protocol via VME/SCL clk 7, init, turn, l 1_accept, pulse, l 1_error VME to TAB/GAB Simple Serial Protocol via VME/SCL clk, frame, addr, data, frame-out, data-out H. Evans TAB/GAB PRR: 7 -Oct-04 7. 6 MHz 16

TAB/GAB Timeline May 03 · VME/SCL prototype received Jun 03 · TAB prototype received TAB/GAB Timeline May 03 · VME/SCL prototype received Jun 03 · TAB prototype received Jul 03 · VME/SCL prototype testing complete (receives SCL signals at DØ) Aug 03 · TAB prototype testing complete Oct 03 · 1 st prototype integration test SCL ADF, TAB; ADF TAB; TAB Cal-Track Feb 04 · GAB prototype received Mar 04 · 2 nd prototype integration test TAB existing L 1 Cal VRB Apr 04 · 2 TABs GAB test May 04 · TAB/GAB crate custom backplane received, installed, tested · GAB prototype testing complete (TAB to GAB & internal) No Layout Problems found with any of the Boards H. Evans TAB/GAB PRR: 7 -Oct-04 17

Internal TAB Testing GAB data TAB Simulation MC Events algo output (Trigger Rate Tool) Internal TAB Testing GAB data TAB Simulation MC Events algo output (Trigger Rate Tool) raw TTs (x-checked w/ tsim_l 1 cal 2 b) Cal-Trk data L 2/L 3 data bit by bit comp TT inputs SW algos 9 Chan Link G-Link raw TTs input mem Global Algos algo output Cal-Trk data TT inputs Chan Link H. Evans raw TTs GAB data Cal-Trk SW algos 0 algo output VME access L 2/L 3 data • all internal connections tested (tau only partially) • using compare’s to debug TAB/GAB PRR: 7 -Oct-04 firmware & simulation 18

Internal GAB Testing MC Events TFW data GAB data TAB Simulation algo output (Trigger Internal GAB Testing MC Events TFW data GAB data TAB Simulation algo output (Trigger Rate Tool) raw TTs Cal-Trk data rcvr output L 2/L 3 data bit by bit comp input mem from TAB G-Link Rcvr 3 input mem rcvr output input mem from TAB L 2/L 3 data Global Chip Rcvr 0 ECL Out TFW data rcvr output input data • O(10? ? ) events tested (rcvr Global) those lines tested • Global ECL Xmit signals tested with ECL Test Card H. Evans TAB/GAB PRR: 7 -Oct-04 19

TAB/GAB I/O þ ADF TAB u Channel Link Parameters s s probed w/ Test TAB/GAB I/O þ ADF TAB u Channel Link Parameters s s probed w/ Test Card insensitive to: PLL range, deskew, DC balance, preemphasis Clock (MHz) 50 u u <3. 7 e-15 At DØ w/ ADF s s u H. Evans <3. 0 e-15 90 extensively exercised at Nevis and DØ used in ADF TAB tests <2. 2 e-15 75 u <1. 1 e-14 60 þ SCL Timing & VME BER Limit error free (parity) xmit for >15 minutes working on bit-by-bit check Use of Channel Link provides clear spec ! TAB/GAB PRR: 7 -Oct-04 20

TAB/GAB I/O (cont) þ TAB L 2/L 3 u u several events sent to TAB/GAB I/O (cont) þ TAB L 2/L 3 u u several events sent to L 1 Cal VRB under DØ timing TAB events to tape soon þ TAB GAB u LVDS transmission checked w/ Test Card s u u safety margin of >400 ps >109 events TAB GAB O(106) events 2 TABs GAB ¨ GAB TFW þ TAB Cal-Track u u sync’ed TAB output w/ L 1 Muon board at DØ varied TAB output & saw corr. variation in L 1 Muon Trigger rate u Signal paths checked using ECL Test Card ¨ GAB L 2/L 3 u identical to TAB ¨ Latency: SW inp SLDB in = ~630 ns All Internal & External Hardware Paths Checked H. Evans TAB/GAB PRR: 7 -Oct-04 21

Remaining Firmware TAB u u u Tau algorithm to be verified Change to Atlas Remaining Firmware TAB u u u Tau algorithm to be verified Change to Atlas EM algo ? Finalize L 2 output Finalize monitoring Simulation of full TAB GAB u Only skeleton of Global chip firmware exists Need to add s s s H. Evans Trigger Terms Monitoring L 2 output TAB/GAB PRR: 7 -Oct-04 22

What’s Next ? · If we’re given the Green Light – produce: u u What’s Next ? · If we’re given the Green Light – produce: u u 10 TABs 3 GABs Task Dur Start End Delivery of rest of components 2 w 10/11/04 10/22/04 Assemble boards (mainly Columbia administration) 6 w 10/11/04 11/19/04 Test TABs/GABs at Nevis · goal: run fully populated TAB/GAB crate · some dependence of availability of engineers 12 w 11/22/04 02/11/05 · Testing at Fermilab u Have (nearly) enough hardware now for Nevis + DØ Tests s u 2 VME/SCLs; 2 TABs; 1 GAB; 2 TAB/GAB crates Can send out some new boards as they pass tests H. Evans TAB/GAB PRR: 7 -Oct-04 23

Conclusions We believe that we’re ready to assemble u hardware has been checked s Conclusions We believe that we’re ready to assemble u hardware has been checked s u u no changes from prototype all components ordered (most arrived) + PCBs here money is in hand (Hal’s CAREER grant) Risks of Going Forward u u TAB: essentially none GAB: some hardware paths not yet fully tested Risks of Delay u u PCBs are aging (produced ~1 year ago) Atlas efforts intensifying THANKS to the Committee for their Help ! H. Evans TAB/GAB PRR: 7 -Oct-04 24

Extra Slides H. Evans TAB/GAB PRR: 7 -Oct-04 25 Extra Slides H. Evans TAB/GAB PRR: 7 -Oct-04 25

“ 2 x 2” EM Algo Simple “ 1 x 2 or 2 x “ 2 x 2” EM Algo Simple “ 1 x 2 or 2 x 1” Algorithm Serial Adders EM(0, 0) EM(0, 1) LM Finder EM(1, 0) EM(1, 1) “ 1 x 2 or 2 x 1” EM Algo Serial Adders H. Evans EM(0, 0) Serial Comparators LM Finder EM(0, 1) EM(1, 0) Had Isolation X EM(0, 0) • No extra latency EM Isolation Ro. I / EM cluster • Chosen cluster still indexed by LL corner of 2 x 2 region TAB/GAB PRR: 7 -Oct-04 26

Data in the TAB H. Evans TAB/GAB PRR: 7 -Oct-04 27 Data in the TAB H. Evans TAB/GAB PRR: 7 -Oct-04 27

SW to Global Chip Data EM/Jet/Tau Results u i for each algo & = SW to Global Chip Data EM/Jet/Tau Results u i for each algo & = 2, 3, 4, 5 send out 12 -bit word encoding highest threshold (7 -1 or 0=none) passed by each of the four ’s in that 11 09 08 06 highest thr =4 highest thr =5 Global Sums u 12 words 05 03 highest thr =3 02 00 highest thr =2 4 words for each = 2, 3, 4, 5 send out 12 -bit word containing EM+HD over four ’s in that 11 00 ET (EM+HD) over = 2, 3, 4, 5 i Simulation Code for all this 1. 2. H. Evans tsim_l 1 cal 2 b standalone relies on DØ software environ. being tested w/ hardware TAB/GAB PRR: 7 -Oct-04 28

TAB to GAB Data · EM/Jet/Tau Results 36 words u for each algo & TAB to GAB Data · EM/Jet/Tau Results 36 words u for each algo & = 2, 3, 4, 5 send out encoded 12 -bit words for = S, C, N containing 2 -bit counts of no. of objects passing each of 6 thresholds i j 11 10 cnt thr-6 09 08 07 cnt thr-5 06 cnt thr-4 05 04 cnt thr-3 03 02 cnt thr-2 01 00 cnt thr-1 i = 2, 3, 4, 5 ; j = S, C, N · Global Sums 3 words 11 00 2 -5 0 -39 ET (EM+HD) 2 -5 0 -39 Ex (EM+HD) 2 -5 0 -39 Ey (EM+HD) H. Evans TAB/GAB PRR: 7 -Oct-04 29

Data to Cal-Track Match Output from TAB Global Chip (10) No. Bits 15 – Data to Cal-Track Match Output from TAB Global Chip (10) No. Bits 15 – 08 Bits 07 – 00 1 JET Mask: = i+3 EM Mask: = i+3 2 JET Mask: = i+2 EM Mask: = i+2 3 JET Mask: = i+1 EM Mask: = i+1 4 JET Mask: = i EM Mask: = i 5 0 0 6 0 0 7 Longitudinal Parity Mask Definition: u u Bit 07 Bits 06 – 00 unused set if threshold j is passed www. nevis. columbia. edu/~evans/l 1 cal/hardware/tab_to_caltrack. html H. Evans TAB/GAB PRR: 7 -Oct-04 30

Short Term Plans Task Comments Timescale Simulation Shift studies into high gear now TAB Short Term Plans Task Comments Timescale Simulation Shift studies into high gear now TAB L 2/L 3 Write data to tape (test unpacking) Oct ADFv 1 TAB Long Term Data Transfer Tests Oct TAB/GAB Fully Automated Event Verification Nov GAB Implement 1 st And/Or terms End 04 ADFv 2 TAB First Integration End 04 H. Evans TAB/GAB PRR: 7 -Oct-04 31

Road to Installation (Jul 05) 1. Operations & Stability a. b. c. d. e. Road to Installation (Jul 05) 1. Operations & Stability a. b. c. d. e. crashes/deadtime reliable downloading monitoring tools param determination unpacker/reco stable run test system meas. in test syst. use in test syst. software in place data from test syst 2. Trigger Quality data & MC a. rates & efficiencies pred w/ MC – verify w/ data b. trigger definitions (L 1, L 2, L 3) in place well beforehand s filter coeff’s, thresholds, and/or terms, trigger list Note: all of these must be Documented H. Evans TAB/GAB PRR: 7 -Oct-04 32

Testing Trigger Quality Splitters Data Available before Installation u at most 16 -EM + Testing Trigger Quality Splitters Data Available before Installation u at most 16 -EM + 16 -H cannot test Sliding Windows Possible Chain to Rate/Eff Estimates 1. Define Triggers s trig-list, and/or, thresh, filt. coeff’s 2. Using Splitter Data derive TT response s s compare ADF Et(TT) output w/ Precision Readout correct MC modeling of Et(TT) probe pathological cases using TWG 3. MC models TAB Algorithms s s sliding windows algorithm is deterministic use standalone MC to look for algorithm pathologies 4. MC models And/Or terms & Trigger List Rates & Eff’s s H. Evans need to test QCD MC vs. Data w/ Run IIa Trigger TAB/GAB PRR: 7 -Oct-04 33