Скачать презентацию SRS News SRU Revision New Hybrids DTC Firmware Скачать презентацию SRS News SRU Revision New Hybrids DTC Firmware

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SRS News SRU Revision, New Hybrids, DTC, Firmware, … Sorin Martoiu, CERN PH/DT 20/02/12 SRS News SRU Revision, New Hybrids, DTC, Firmware, … Sorin Martoiu, CERN PH/DT 20/02/12 SRS News, Sorin Martoiu, CERN 2012, 9 th RD 51 Collaboratin Meeting 1

Outline n n SRU revision 2 (PCB produced, assembly) New Hybrids New APV Hybrids Outline n n SRU revision 2 (PCB produced, assembly) New Hybrids New APV Hybrids produced (micro HDMI connector) ¨ VFAT 2 and BEETLE hybrids under design ¨ n SRS Firmware Evolution ¨ n n New APV firmware options (Zero-suppression code) Design of the DTC link ¨ n New features for near-future upgrades LVDS channel tests Towards an industrial SRS design 20/02/12 SRS News, Sorin Martoiu, CERN 2012, 9 th RD 51 Collaboratin Meeting 2

SRU rev 2 SRU revision 1 features: 4 x SFP+ (Gb. E, ALICE DDL, SRU rev 2 SRU revision 1 features: 4 x SFP+ (Gb. E, ALICE DDL, ATLAS S-Link, …) ü SO-DIMM DDR 3 (2 GB) ü TTC ü Remote configuration (BPI Flash) ü SRU revision 2 upgrades: 10 Gb. E PHY n 3 x SFP+ (up to 5 Gbps each) n Jitter-cleaner PLL for TTCrx clock ( < 50 ps peak-to-peak jitter) n 20/02/12 SRS News, Sorin Martoiu, CERN 2012, 9 th RD 51 Collaboratin Meeting 3

3 x SFP+ 10 Gb. E SRU rev 2 New 10 Gb. E PHY 3 x SFP+ 10 Gb. E SRU rev 2 New 10 Gb. E PHY DDR 3 SODIMM New PLL (TTC CLK) Virtex 6 FPGA 20/02/12 SRS News, Sorin Martoiu, CERN 2012, 9 th RD 51 Collaboratin Meeting 4

New Hybrids n New APV Hybrid n VFAT 2 Hybrid n BEETLE Hybrid New New Hybrids n New APV Hybrid n VFAT 2 Hybrid n BEETLE Hybrid New Micro HDMI connector 20/02/12 • Initial production yield < 90% • Some simple assembly issues and some test samples included in the yield. • Final result may improve SRS News, Sorin Martoiu, CERN 2012, 9 th RD 51 Collaboratin Meeting 5

New Hybrids n New APV Hybrid n VFAT 2 Hybrid n BEETLE Hybrid • New Hybrids n New APV Hybrid n VFAT 2 Hybrid n BEETLE Hybrid • 2 hybrid versions (with or without discharge protection) • Power via detector PCB (option) • Signals via detector PCB (option for the short version only) • One hybrid per HDMI cable • Work in progress (layout finalization) 20/02/12 SRS News, Sorin Martoiu, CERN 2012, 9 th RD 51 Collaboratin Meeting 6

New Hybrids n New APV Hybrid n VFAT 2 Hybrid n BEETLE Hybrid • New Hybrids n New APV Hybrid n VFAT 2 Hybrid n BEETLE Hybrid • Under design at Weizmann Institute, Israel • Comparator output OR/MUX via radtol CPLD • Master-slave versions for analog readout mode • Work in progress (layout finalization) 20/02/12 SRS News, Sorin Martoiu, CERN 2012, 9 th RD 51 Collaboratin Meeting 7

Firmware Evolution n Test modules ¨ n DTC Link ¨ n Protocol definition Synch Firmware Evolution n Test modules ¨ n DTC Link ¨ n Protocol definition Synch Module (clock synchronization of multiple FEC cards) ¨ ¨ ¨ n Used for QA tests in manufacture process On-board clock (free running) DTC clock (SRU clock) Ethernet clock (TX clock of the Network Switch) Design Partitioning (Xilinx tool migration) ¨ ¨ 20/02/12 Easy integration of new applications/front-ends Partial reconfiguration of the application module (limited support for Virtex 5 family) SRS News, Sorin Martoiu, CERN 2012, 9 th RD 51 Collaboratin Meeting 8

Firmware Evolution Voltage o. C EEPROM On-board clock App Slow Control Readout Control FE Firmware Evolution Voltage o. C EEPROM On-board clock App Slow Control Readout Control FE FE Card Data Packet Interface Processor Builder Application Layer (Reconfigurable partition*) DTC clock Ethernet clock DTC Link SC BUS Clock Unit Test & Init Ethernet Core System SC SC Core Monitoring Data path Current DAQ System Layer (Fixed partition) * Xilinx dynamic reconfiguration support is limited for Virtex 5 FPGAs 20/02/12 SRS News, Sorin Martoiu, CERN 2012, 9 th RD 51 Collaboratin Meeting 9

APV Signal Processor 50 k. B Designed by Raffaele Giordano, INFN Napoli BYPASS 50 APV Signal Processor 50 k. B Designed by Raffaele Giordano, INFN Napoli BYPASS 50 k. B - Frame Decode - Pedestal Corr. - Zero Suppress. Event Build 0 - 3 k. B/ch 50 k. B Warnings: Additional Features: n. Clock phase calibration n. Pedestal and noise calibration n. Double input buffer (samples < 15) n. Common-mode channel (future) 20/02/12 • Due to resource limitations the (old) raw ADC mode and Zero-suppression mode cannot be implemented in a single firmware version. • A single channel bypass mode is provided • Common mode rejection not implemented. A commonmode channel output is foreseen for later revision SRS News, Sorin Martoiu, CERN 2012, 9 th RD 51 Collaboratin Meeting 10

Clock phase calibration n Wrong clock-edge sampling; resync using the on-hybrid PLL 25 chip Clock phase calibration n Wrong clock-edge sampling; resync using the on-hybrid PLL 25 chip 20/02/12 SRS News, Sorin Martoiu, CERN 2012, 9 th RD 51 Collaboratin Meeting 11

APV Frame Decoder Analogue data (128 channel samples) sync pulses 20/02/12 headers SRS News, APV Frame Decoder Analogue data (128 channel samples) sync pulses 20/02/12 headers SRS News, Sorin Martoiu, CERN 2012, 9 th RD 51 Collaboratin Meeting 12

APV Zero Suppression Analogue data (128 channel samples) • Pedestal correction • Zero suppression APV Zero Suppression Analogue data (128 channel samples) • Pedestal correction • Zero suppression (integral discrimination) • Thresholds are automatically calculated from noise data • User can read or write pedestal and noise data via slow-controls 20/02/12 SRS News, Sorin Martoiu, CERN 2012, 9 th RD 51 Collaboratin Meeting 13

DTC Links SRU 40 x DTC links • 2 x LVDS TX (clock, trigger, DTC Links SRU 40 x DTC links • 2 x LVDS TX (clock, trigger, control) • 2 x LVDS RX (data, trigger, control) Physical Interface • LVDS buffers (< 2 Gbps, no signal conditioning) • CAT 5 E/6/7 FTP 20/02/12 SRS News, Sorin Martoiu, CERN 2012, 9 th RD 51 Collaboratin Meeting 14

DTC LVDS Link Tests 100 MHz DDR PRBS pattern (400 Mbps) 2. 5 m DTC LVDS Link Tests 100 MHz DDR PRBS pattern (400 Mbps) 2. 5 m 2. 5 + 15 m 20/02/12 2. 5 + 10 m 26 m SRS News, Sorin Martoiu, CERN 2012, 9 th RD 51 Collaboratin Meeting 15

DTC LVDS Tests (Preliminary) Cable Length Cable Type Max Speed 1 2. 5 m DTC LVDS Tests (Preliminary) Cable Length Cable Type Max Speed 1 2. 5 m CAT-5 E UTP 700 MHz 2 2. 80 Gbps 2. 24 Gbps 2. 5 + 10 m CAT-5 E FTP 460 MHz 1. 84 Gbps 1. 47 Gbps 2. 5 + 15 m CAT-6 UTP 300 MHz 3 1. 20 Gbps 0. 96 Gbps 26 m CAT-7 FTP 200 MHz 0. 80 Gbps 0. 64 Gbps 3 1 Only Ø 50 m DTC link not feasible Ø Signal conditioners might be an option Ø Data bandwidth higher than expected at moderate cable length ( > 1 Gbps) 20/02/12 Bandwidth (Gbps) one FEC card tested. Results may be different for a representative population; 2 FPGA design limit 3 Failed at 280 MHz. Safe value 260 MHz (1. 04 Gbps; 0. 8 Gbps effective) Raw Data Bandwidth (20% Bandwidth protocol overhead) 2. 5 2 1. 5 1 0. 5 0 0 5 10 15 20 25 Cable Length (m) SRS News, Sorin Martoiu, CERN 2012, 9 th RD 51 Collaboratin Meeting 30 35 16

DTC Protocol Proposal Ch. request Flow control Framing Control ctrl High priority ch. Trigger/Busy/… DTC Protocol Proposal Ch. request Flow control Framing Control ctrl High priority ch. Trigger/Busy/… Low priority ch. Data/Control n 8 b/10 b DTC TX commas 10 b/8 b Latency correction DTC RX Trigger, busy, … transmitted with high priority and guarantied fixed latency. Data transmitted over regular (low priority) channel. 8 b/10 b encoding Ø Ø Ø ⚠ n commas Channel interleaving ¨ ¨ n Frame detection DC balance (improves channel performance) Error detection “Out-of-band” signaling (comma characters – synchronization, framing control, …) 20% overhead Versatile Design (Auto-negotiation, full control of slave DTC via SRU) 20/02/12 SRS News, Sorin Martoiu, CERN 2012, 9 th RD 51 Collaboratin Meeting 17

DTC Protocol Proposal 20/02/12 SRS News, Sorin Martoiu, CERN 2012, 9 th RD 51 DTC Protocol Proposal 20/02/12 SRS News, Sorin Martoiu, CERN 2012, 9 th RD 51 Collaboratin Meeting 18

SRS in Industrial Standard Advanced. TCA Discussions with EICSYS Gmb. H (Hamburg) studying the SRS in Industrial Standard Advanced. TCA Discussions with EICSYS Gmb. H (Hamburg) studying the possibility to develop SRS systems in industrial standards (ATCA, m. TCA, . . ) • Full industrial certification (CE, mechanical, EMI, …) • Runtime reliability (>99. 9% uptime) • System Management 20/02/12 SRS News, Sorin Martoiu, CERN 2012, 9 th RD 51 Collaboratin Meeting 19

Thank you! 20/02/12 SRS News, Sorin Martoiu, CERN 2012, 9 th RD 51 Collaboratin Thank you! 20/02/12 SRS News, Sorin Martoiu, CERN 2012, 9 th RD 51 Collaboratin Meeting 20

Additional Slides 20/02/12 SRS News, Sorin Martoiu, CERN 2012, 9 th RD 51 Collaboratin Additional Slides 20/02/12 SRS News, Sorin Martoiu, CERN 2012, 9 th RD 51 Collaboratin Meeting 21

SRS and structures definition. Format ZS Data types typedef unsigned char BYTE; unsigned int SRS and structures definition. Format ZS Data types typedef unsigned char BYTE; unsigned int WORD 32; unsigned short int WORD 16; signed short int INT 16; struct APV_HEADER { BYTE APV_ID; BYTE N_CHANNELS; BYTE N_SAMPLES; BYTE ZS_ERROR; WORD 16 FLAGS; WORD 32 RESERVED; // // // 8 -bit word 32 -bit word 16 -bit signed int APV Identifier number on the FEC card (0 to 15) the number of channels which will be following the header the number of samples per channel Error code from the Zero Suppression Block, meaning have to be defined bit 0 : ‘ 0’ – Classic zero suppression, ‘ 1’ – Zero suppression with peak finding bits 1 to 15 are still reserved for future use 32 bits reserved for future use }; struct CHAN_INFO { BYTE RESERVED; BYTE CHAN_ID; INT 16 CHANDATA[N_SAMPLES]; // // // 8 -bits reserved for future use Channel identifier, APV physical channels are 0 to 127, 128 could be used for the common mode average 129 for error codes from the APV (pipeline address(8 bits) & error bit) 16 bit words, actual data will be 13 -bits wide }; 20/02/12 Author: Raffaele Giordano Ver. 0 25 Jan. 2012 22

Read-out Sequence APV Header CHAN_INFO 20/02/12 At each read-out from the ZS buffer for Read-out Sequence APV Header CHAN_INFO 20/02/12 At each read-out from the ZS buffer for a given APV, the ZS will answer with this sequence. N_CHANNELS CHAN_INFO structures 1. In classic zero suppression mode, the CHANDATA array contains the actual samples. 2. In peak finding mode, the CHANDATA array has always two elements: CHANDATA[0] = peak value CHANDATA[1] = peak time Author: Raffaele Giordano Ver. 0 25 Jan. 2012 23