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From 4 -bit micros to Multi-cores: A brief history, Future Challenges, and how CEs From 4 -bit micros to Multi-cores: A brief history, Future Challenges, and how CEs can prepare for them Ganesh Gopalakrishnan, School of Computing, University of Utah • NSF CSR-SMA: Toward Reliable and Efficient Message Passing Software Through Formal Analysis (the ``Gauss'' project) • 2005 -TJ-1318 (SRC/Intel Customization), Scaling Formal Methods Towards Hierarchical Protocols in Shared Memory Processors (the ``MPV'' project) • Microsoft HPC Innovation Center, ``Formal Analysis and Code Generation Support for MPI'' 1

Microprocessors are everywhere! 2 Microprocessors are everywhere! 2

“Desktops” turn into supercomputers 8 die x 2 CPUs x 2 -way execution = “Desktops” turn into supercomputers 8 die x 2 CPUs x 2 -way execution = 32 -way shared memory machine! 3

Supercomputers have become fundamental tools that underlie all of engineering (Blue. Gene/L - Image Supercomputers have become fundamental tools that underlie all of engineering (Blue. Gene/L - Image courtesy of IBM / LLNL) (Image courtesy of Steve Parker, CSAFE, Utah) 4

From Simulation to Flight: Virtual Roll-out of Boeing 787 “Dreamliner” Entire Airplane being Designed From Simulation to Flight: Virtual Roll-out of Boeing 787 “Dreamliner” Entire Airplane being Designed and Flown inside a Computer (Simulation Program). The first plane to fly is the real one (not a mockup model). (Photo courtesy of Boeing. ) 5

This Talk n Some history q q n The future q q n How This Talk n Some history q q n The future q q n How the micro came about Past predictions Multicores Hardware Challenges Programming them How I am trying to help (my own research) General awareness q q International matters Tips to survive, … and to excel 6

The birth of the micro n n n Intel’s 4004 and TI’s TMS-1000 were The birth of the micro n n n Intel’s 4004 and TI’s TMS-1000 were the first 4004 – with cover removed (L) and on (R) Patent awarded to TI ! Intel made single-chip computer for Datapoint Marketed it as 8008 when Datapoint did not use the design 7

Revolution of the 70 s and 80 s n n Intel : 4004, 4040, Revolution of the 70 s and 80 s n n Intel : 4004, 4040, 8008, 8080, 8085, 8086, 80186, 80286, 80386, 80486, Pentium, PPro, … now “X 86” (also Itanium) Motorola: 6800, 6810, 6820, 68000, 68010, 68020, … then Power. PC (collab with IBM) Other companies Burst of activity – EVERY student wanted to build an embedded computer out of a micro in the 70 s and 80 s. 8

The micro killed the mini n It became amply clear in the 80 s The micro killed the mini n It became amply clear in the 80 s that it was going to replace “mainframes” q casual experiments conducted between Sun-2 (68020) versus Digital’s VAX 11/750 and 780 n The birth of the IBM PC around 1980 started things going mu-P’s way! n With the masses having a PC each, the Internet could be meaningfully reborn! 9

… and is in every supercomputer n n John Hennessy’s prediction during SC’ 97: … and is in every supercomputer n n John Hennessy’s prediction during SC’ 97: (http: //newsservice. stanford. edu/news/1997/november 19/s upercomp 1119. html John Hennessy: “Today’s microprocessor chipping away at supercomputer market” q n Traditionally designed supercomputers will vanish within a decade – it has! Clusters of them fill vast rooms now! 10

IBM ASCI White Machine Released in 2000 -- Peak Performance : 12. 3 teraflops. IBM ASCI White Machine Released in 2000 -- Peak Performance : 12. 3 teraflops. -- Processors used : IBM RS 6000 SP Power 3's - 375 MHz. -- There are 8, 192 of these processors -- The total amount of RAM is 6 Tb. -- Two hundred cabinets - area of two basket ball courts. 11

IBM Blue. Gene/L The first machine in the family, Blue Gene/L, is expected to IBM Blue. Gene/L The first machine in the family, Blue Gene/L, is expected to operate at a peak performance of about 360 teraflops (360 trillion operations per second), and occupy 64 racks -- taking up only about the same space as half of a tennis court. Researchers at the Lawrence Livermore National Laboratory (LLNL) plan to use Blue Gene/L to simulate physical phenomena that require computational capability much greater than presently available, such as cosmology and the behavior of stellar binary pairs, laser-plasma interactions, and the behavior and aging of high explosives. 12

Now it’s the era of Multi-cores: e. g. , Sun Niagara processor 8 CPU Now it’s the era of Multi-cores: e. g. , Sun Niagara processor 8 CPU cores (80 cores demoed by Intel already…) 13

Energy advantages of multicores q q Putting two simple CPUs achieves 80% performance per Energy advantages of multicores q q Putting two simple CPUs achieves 80% performance per cpu with only 50% of the power per CPU chip as a whole gives 1. 6 x performance for same power PROVIDED we can keep the cores busy Simple way to keep ‘em busy n n q Virus-checker in background while user computes Photoshop in one and Windows on another More complex ways to keep multiple cores busy are being investigated 14

So what are the design issues? Lots! Here is a small subset: 1. Complex So what are the design issues? Lots! Here is a small subset: 1. Complex cache coherence protocols ! 2. Silicon debugging is becoming a headache ! 3. Programming apps is becoming hard ! 4. The “Digital Divide” 15

1. Dual and Quad-cores are the norm these days. Their caches are visibly central 1. Dual and Quad-cores are the norm these days. Their caches are visibly central > 80% of chips shipped will be multi-core (photo courtesy of Intel Corporation. ) 16

What is cache coherence? n n Illusion of global shared memory is preferred Need What is cache coherence? n n Illusion of global shared memory is preferred Need mechanisms to keep caches consistent q Every read must fetch the data written by the latest write P 1 P 2 read(a) write(a, 1) … …. read(a) write(a, 2) 17

What is cache coherence? n n Illusion of global shared memory is preferred Need What is cache coherence? n n Illusion of global shared memory is preferred Need mechanisms to keep caches consistent q Every read must fetch the data written by the latest write P 1 P 2 read(a, 2) write(a, 1) … …. read(a, 1) write(a, 2) With a coherent cache, the indicated outcome is not allowed 18

What is cache coherence? n n Illusion of global shared memory is preferred Need What is cache coherence? n n Illusion of global shared memory is preferred Need mechanisms to keep caches consistent q Every read must fetch the data written by the latest write P 1 P 2 read(a, 2) write(a, 1) … …. read(a, 2) write(a, 2) But this outcome is allowed 19

Cache Coherence Protocol Verification My “MPV” research project develops techniques to ensure that cache Cache Coherence Protocol Verification My “MPV” research project develops techniques to ensure that cache coherence protocols are correct We use an approach called Model Checking We control the complexity of model checking thru the Assume / Guarantee approach Intra-cluster protocols Chip-level protocols … mem dir mem Inter-cluster protocols 20

A caching hierarchy such as this is too hard to verify Remote Cluster 1 A caching hierarchy such as this is too hard to verify Remote Cluster 1 L 1 Cache Home Cluster L 1 Cache Remote Cluster 2 L 1 Cache L 2 Cache+Local Dir RAC RAC Global Dir Main Memory 21

So we create several “mutually supporting” abstractions Home Cluster Remote Cluster 1 L 1 So we create several “mutually supporting” abstractions Home Cluster Remote Cluster 1 L 1 Cache Remote Cluster 2 L 2 Cache+Local Dir’ RAC RAC Global Dir Main Memory 22

Abstracted Protocol #2 Remote Cluster 1 L 1 Cache Home Cluster Remote Cluster 2 Abstracted Protocol #2 Remote Cluster 1 L 1 Cache Home Cluster Remote Cluster 2 L 2 Cache+Local Dir’ RAC RAC Global Dir Main Memory 23

Problem 2: Silicon Debugging: Can’t see “inside” CPUs without paying a huge price • Problem 2: Silicon Debugging: Can’t see “inside” CPUs without paying a huge price • On-chip instrumentation is one way to “see” what is inside • One must put in several built-in test circuits • One must design with the option of bypassing new features cpu Visible “miss” traffic cpu Invisible “miss” traffic 24

3: Programming Apps is hard! e. g. threads Thread and process interactions need to 3: Programming Apps is hard! e. g. threads Thread and process interactions need to coordinate Otherwise something analogous to this will happen ! Teller 1 Teller 2 Read bank balance ($100) Read bank balance ($100) Add $10 on scratch paper ($110) Subtract $10 on scratch paper ($90) Enter $110 into account Enter $90 into account USER LEFT WITH $90 – NOT WITH $100 !! 25

Programming Msg. Passing Supercomputers can be quite tricky My “Gauss” project (in collaboration with Programming Msg. Passing Supercomputers can be quite tricky My “Gauss” project (in collaboration with Robert M. Kirby) ensures that supercomputer programs do not contain bugs, and also perform efficiently Virtually all supercomputers are programmed using the “MPI” communication library Mis-using this library can often result in bugs that show up only after porting P 1 P 2 MPI_SEND(to P 2, Msg) MPI_SEND(to P 1, Msg) MPI_RECV(from P 2, Msg) MPI_RECV(from P 1, Msg) If the system does not provide sufficient buffering, the sends may both block, thus causing a deadlock ! 26

Simulation code that does automatic load balancing is difficult to write and debug (Photo Simulation code that does automatic load balancing is difficult to write and debug (Photo courtesy NHTSA) 27

LOTS of hard problems remain open n How to provide memory bandwidth? q q LOTS of hard problems remain open n How to provide memory bandwidth? q q q Put multicore CPU chip on top of highly dense DRAM chip (e. g. 8 GB) Most users will buy just “one of those” Others will buy SDRAM module add-ons n n q Slow access for now Optical interconnect is an active research area Higher memory bandwidth solutions coming n So the real challenge remains programming! q Insights from recent Microsoft visit 28

Emerging Programming Paradigms n n n Microsoft’s Task Pallallel Library Intel’s Thread Building Blocks Emerging Programming Paradigms n n n Microsoft’s Task Pallallel Library Intel’s Thread Building Blocks Open. MP, Cluster Open. MP, Cuda, Cilk Transaction memories Special purpose paradigms q q LINQ and PLINQ for Relational Databases Game Programming: roll customized solutions 29

Emerging Programming Paradigms n Transaction Memories! q q q Users cause too many bugs Emerging Programming Paradigms n Transaction Memories! q q q Users cause too many bugs when programming using locks Transaction memories allow shared memory threads to “watch” each others read/write actions Conflicting accesses can rollback and retry 30

Problem 4: Huge! The “digital divide” Need plenty of Outreach n Better CE / Problem 4: Huge! The “digital divide” Need plenty of Outreach n Better CE / CS projects in SLVSEF n Mentoring 31

Learn from History – Learn Computer History n If you want to understand today, Learn from History – Learn Computer History n If you want to understand today, you have to search yesterday. ~Pearl Buck n Things are changing SO fast that basic principles are often being diluted n Get excited by studying computer history and seeing how much better off we are (also be chagrined by all the lost opportunity!) 32

Where to learn computer history? n Computer History Museum, Mountain View n Intel Museum, Where to learn computer history? n Computer History Museum, Mountain View n Intel Museum, Santa Clara n Boston Computer Museum n Many in the UK (Manchester, London, …) n Travel widely – be inspired by what you see! 33

It is important to understand the International Scene n Lessons from MSR India q It is important to understand the International Scene n Lessons from MSR India q q n Lessons from Intel India q q n Amazing talent-pool Relatively high availability of talent Talent-pool still lacks depth and abilities of many of our CEs We can stay competitive in hardware for a LONG time to come Apply for international internships! 34

Gradual loss of manufacturing death n n Lots of manufacturing happening outside the US Gradual loss of manufacturing death n n Lots of manufacturing happening outside the US Fear not – CE / CS jobs are still on the rise q n Huge demand forecast within the US THE REAL DANGER q Loss of manufacturing kills pride and incentive to learn – we don’t want that in CE 35

Recipe for success n The best ideas don’t always work q q n Quiet Recipe for success n The best ideas don’t always work q q n Quiet tenacity q q n n Wait for the world to be ready for the ideas The devil is in the detail Too much established momentum Decide goal (short-term impact vs. long-term) Tenacity without ruffling feathers needlessly Work hard! work smart! learn theory! be a champion algorithm / program designer! learn advanced hardware design! Learn to write extremely clearly and precisely! Learn to give inspiring talks! (be inspired first!) 36