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ELEC 2041 Microprocessors and Interfacing Lectures 31: Cache Memory - I http: //webct. edtec. ELEC 2041 Microprocessors and Interfacing Lectures 31: Cache Memory - I http: //webct. edtec. unsw. edu. au/ May 2006 Saeid Nooshabadi [email protected] edu. au ELEC 2041 lec 31 -Cache-I. 1 Some of the slides are adopted from David Patterson (UCB) Saeid Nooshabadi

Outline ° Memory Hierarchy ° On-Chip SRAM ° Direct-Mapped Cache ELEC 2041 lec 31 Outline ° Memory Hierarchy ° On-Chip SRAM ° Direct-Mapped Cache ELEC 2041 lec 31 -Cache-I. 2 Saeid Nooshabadi

Review: ARM System Architecture Fast on-Chip RAM External Lower Speed SRAM, Slower DRAM, Much Review: ARM System Architecture Fast on-Chip RAM External Lower Speed SRAM, Slower DRAM, Much Slower Flash-ROM ELEC 2041 lec 31 -Cache-I. 3 Saeid Nooshabadi

Memory Hierarchy (#1/5) ° Processor • executes programs • runs on order of nanoseconds Memory Hierarchy (#1/5) ° Processor • executes programs • runs on order of nanoseconds to picoseconds • needs to access code and data for programs: where are these? ° Disk • HUGE capacity (virtually limitless) • VERY slow: runs on order of milliseconds • so how do we account for this gap? ELEC 2041 lec 31 -Cache-I. 4 Saeid Nooshabadi

Memory Hierarchy (#2/5) ° Memory (DRAM) • smaller than disk (not limitless capacity) • Memory Hierarchy (#2/5) ° Memory (DRAM) • smaller than disk (not limitless capacity) • contains subset of data on disk: basically portions of programs that are currently being run • much faster than disk: memory accesses don’t slow down processor quite as much • Problem: memory is still too slow (hundreds of nanoseconds) • Solution: add more layers - On-chip Memory - On-chip Caches ELEC 2041 lec 31 -Cache-I. 5 Saeid Nooshabadi

Memory Hierarchy (#3/5) Processor Increasing Higher Distance from Proc. , Levels in Level 1 Memory Hierarchy (#3/5) Processor Increasing Higher Distance from Proc. , Levels in Level 1 Decreasing memory Level 2 cost / MB hierarchy Level 3. . . Level n Lower Size of memory at each level ELEC 2041 lec 31 -Cache-I. 6 Saeid Nooshabadi

Memory Hierarchy (#4/5) Hard Disk RAM/ROM DRAM EEPROM Processor Control Speed: Fastest Size: Smallest Memory Hierarchy (#4/5) Hard Disk RAM/ROM DRAM EEPROM Processor Control Speed: Fastest Size: Smallest Cost: Highest ELEC 2041 lec 31 -Cache-I. 7 Memory Registers Memory Datapath Memory Cache L 1 SRAM Cache L 2 SRAM Slowest Biggest Lowest Saeid Nooshabadi

Memory Hierarchy (#5/5) ° If level is closer to Processor, it must be: • Memory Hierarchy (#5/5) ° If level is closer to Processor, it must be: • smaller • faster • subset of all lower levels (contains most recently used data) • contain at least all the data in all higher levels ° Lowest Level (usually disk) contains all available data ELEC 2041 lec 31 -Cache-I. 8 Saeid Nooshabadi

Memory Hierarchy Computer Processor Memory Devices (active) (passive) Input Control (where (“brain”) programs, Output Memory Hierarchy Computer Processor Memory Devices (active) (passive) Input Control (where (“brain”) programs, Output Datapath data live (“brawn”) when running) Keyboard, Mouse Disk, Network Display, Printer ° Purpose: • Faster access to large memory from processor ELEC 2041 lec 31 -Cache-I. 9 Saeid Nooshabadi

Memory Hierarchy Analogy: Library (#1/2) ° You’re writing an assignment paper (Processor) at a Memory Hierarchy Analogy: Library (#1/2) ° You’re writing an assignment paper (Processor) at a table in the Library ° Library is equivalent to disk • essentially limitless capacity • very slow to retrieve a book ° Table is memory • smaller capacity: means you must return book when table fills up • easier and faster to find a book there once you’ve already retrieved it ELEC 2041 lec 31 -Cache-I. 10 Saeid Nooshabadi

Memory Hierarchy Analogy: Library (#2/2) ° Open books on table are on-chip memory/cache • Memory Hierarchy Analogy: Library (#2/2) ° Open books on table are on-chip memory/cache • smaller capacity: can have very few open books fit on table; again, when table fills up, you must close a book • much, much faster to retrieve data ° Illusion created: whole library open on the tabletop • Keep as many recently used books open on table as possible since likely to use again • Also keep as many books on table as possible, since faster than going to library shelves ELEC 2041 lec 31 -Cache-I. 11 Saeid Nooshabadi

Memory Hierarchy Basis ° Disk contains everything. ° When Processor needs something, bring it Memory Hierarchy Basis ° Disk contains everything. ° When Processor needs something, bring it into to all higher levels of memory. ° On-chip Memory/Cache contains copies of data in memory that are being used. ° Memory contains copies of data on disk that are being used. ° Entire idea is based on Temporal Locality: if we use it now, we’ll want to use it again soon (a Big Idea) ELEC 2041 lec 31 -Cache-I. 12 Saeid Nooshabadi

On Chip SRAM Memory ° Provides fast (zero wait state access to program and On Chip SRAM Memory ° Provides fast (zero wait state access to program and data) ° It occupies a portion of address space. ° Requires explicit management by the programmers. • Part of the program has to copy itself from slow external slow memory (eg flash-rom), into the internal on-chip ram and start executing from there • Works well for limited number of programs where, the program behaviour and space requirement is well defined. ELEC 2041 lec 31 -Cache-I. 13 Saeid Nooshabadi

DSLMU on-Chip RAM Applications are copied from the FLASH ROM to int. RAM to DSLMU on-Chip RAM Applications are copied from the FLASH ROM to int. RAM to make them go faster External mem area External Flash ROM Works only if there a few well behaved applications App #3 App #2 App #1 Schedul er Int. SRAM ELEC 2041 lec 31 -Cache-I. 14 Saeid Nooshabadi

A Case for Cache ° On-Chip SRAM requires explicit management by the programmer • A Case for Cache ° On-Chip SRAM requires explicit management by the programmer • Possible for an embedded system with small number of well defined programs • Not possible for a general purpose processor with many programs, where the application mix cannot be determined in advance - Explicit memory management become difficult ° We need a mechanism where the copying from the slow external RAM to Int. memory is automated by hardware (Cache!) ELEC 2041 lec 31 -Cache-I. 15 Saeid Nooshabadi

Cache Design ° How do we organize cache? ° Where does each memory address Cache Design ° How do we organize cache? ° Where does each memory address map to? (Remember that cache is subset of memory, so multiple memory addresses map to the same cache location. ) (Books from many shelves are on the same table) ° How do we know which elements are in cache? ° How do we quickly locate them? ELEC 2041 lec 31 -Cache-I. 16 Saeid Nooshabadi

Direct-Mapped Cache (#1/2) ° In a direct-mapped cache, each memory address is associated with Direct-Mapped Cache (#1/2) ° In a direct-mapped cache, each memory address is associated with one possible block within the cache • Therefore, we only need to look in a single location in the cache for the data to see if it exists in the cache • Block is the unit of transfer between cache and memory ELEC 2041 lec 31 -Cache-I. 17 Saeid Nooshabadi

Direct-Mapped Cache (#2/2) Memory Address Memory 0 1 2 3 4 5 6 7 Direct-Mapped Cache (#2/2) Memory Address Memory 0 1 2 3 4 5 6 7 8 9 A B C D E F ELEC 2041 lec 31 -Cache-I. 18 Cache Index 0 1 2 3 4 Byte Direct Mapped Cache ° Block size = 1 byte ° Cache Location 0 can be occupied by data from: • Memory location 0, 4, 8, . . . • In general: any memory location that is multiple of 4 Saeid Nooshabadi

Issues with Direct-Mapped ° Since multiple memory addresses map to same cache index, how Issues with Direct-Mapped ° Since multiple memory addresses map to same cache index, how do we tell which one is in there? ° Store the address information along with the data in the cache Address from the processor tttttttttttttttii address tag to check have correct block Compare address tag with indexed value to check for match index to select block Cache 4 Byte Direct Index Mapped Cache ttttttttttttttt 0 ttttttttttttttt 1 ttttttttttttttt 2 ttttttttttttttt 3 ELEC 2041 lec 31 -Cache-I. 19 Saeid Nooshabadi

Direct-Mapped with 1 Byte Blocks Example block index Address tag address data RAM decoder Direct-Mapped with 1 Byte Blocks Example block index Address tag address data RAM decoder tag RAM compare hit ELEC 2041 lec 31 -Cache-I. 20 data Saeid Nooshabadi

Reading Material ° Steve Furber: ARM System On-Chip; 2 nd Ed, Addison-Wesley, 2000, ISBN: Reading Material ° Steve Furber: ARM System On-Chip; 2 nd Ed, Addison-Wesley, 2000, ISBN: 0 -20167519 -6. Chapter 10. ELEC 2041 lec 31 -Cache-I. 21 Saeid Nooshabadi

Issues with Direct-Mapped with Larger Blocks ° Since multiple memory blocks map to same Issues with Direct-Mapped with Larger Blocks ° Since multiple memory blocks map to same cache index, how do we tell which one is in there? ° How do we select the bytes in the block? ° Result: divide memory address into three fields tttttttttttttttioo tag to check if have correct block ELEC 2041 lec 31 -Cache-I. 22 index byte to offset select within block Saeid Nooshabadi

Direct-Mapped with Larger Blocks Example Address tag ELEC 2041 lec 31 -Cache-I. 23 block Direct-Mapped with Larger Blocks Example Address tag ELEC 2041 lec 31 -Cache-I. 23 block index Byte offset Saeid Nooshabadi

Direct-Mapped Cache Terminology ° All fields are read as unsigned integers. ° Index: specifies Direct-Mapped Cache Terminology ° All fields are read as unsigned integers. ° Index: specifies the cache index (which “row” or “line” of the cache we should look in) ° Offset: once we’ve found correct block, specifies which byte within the block we want ° Tag: the remaining bits after offset and index are determined; these are used to distinguish between all the memory addresses that map to the same location ELEC 2041 lec 31 -Cache-I. 24 Saeid Nooshabadi

Direct-Mapped Cache Example (#1/3) ° Suppose we have a 16 KB of data in Direct-Mapped Cache Example (#1/3) ° Suppose we have a 16 KB of data in a direct-mapped cache with 4 word blocks ° Determine the size of the tag, index and offset fields if we’re using a 32 -bit architecture (ie. 32 address lines) ° Offset • need to specify correct byte within a block • block contains 4 words 16 bytes 24 bytes • need 4 bits to specify correct byte ELEC 2041 lec 31 -Cache-I. 25 Saeid Nooshabadi

Direct-Mapped Cache Example (#2/3) ° Index: (~index into an “array of blocks”) • need Direct-Mapped Cache Example (#2/3) ° Index: (~index into an “array of blocks”) • need to specify correct row in cache • cache contains 16 KB = 214 bytes • block contains 24 bytes (4 words) • # rows/cache = # blocks/cache (since there’s one block/row) = bytes/cache bytes/row = 214 bytes/cache 24 bytes/row = 210 rows/cache • need 10 bits to specify this many rows ELEC 2041 lec 31 -Cache-I. 26 Saeid Nooshabadi

Direct-Mapped Cache Example (#3/3) ° Tag: use remaining bits as tag • tag length Direct-Mapped Cache Example (#3/3) ° Tag: use remaining bits as tag • tag length = mem addr length - offset - index = 32 - 4 - 10 bits = 18 bits • so tag is leftmost 18 bits of memory address ° Why not full 32 bit address as tag? • All bytes within block need same address (-4 b) • Index must be same for every address within a block, so it is redundant in tag check, thus can leave off to save memory (- 10 bits in this example) ELEC 2041 lec 31 -Cache-I. 27 Saeid Nooshabadi

Things to Remember ° We would like to have the capacity of disk at Things to Remember ° We would like to have the capacity of disk at the speed of the processor: unfortunately this is not feasible. ° So we create a memory hierarchy: • each successively lower level contains “most used” data from next lower level • exploits temporal locality ° Locality of reference is a Big Idea ELEC 2041 lec 31 -Cache-I. 28 Saeid Nooshabadi