Скачать презентацию COMP 541 Hierarchical Design Verilog Montek Singh

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COMP 541 Hierarchical Design & Verilog Montek Singh Jan 25, 2012 1

Topics ã Hierarchical Design ã Verilog Primer 2

Design Hierarchy ã Just like with large program, to design a large chip need hierarchy ã Divide and Conquer l To create, test, and also to understand ã Block is equivalent to object 3

Example ã 9 -input odd func (parity for byte) ã Block for schematic is box with labels 4

Design Broken Into Modules Use 3 -input odd functions 5

Each Module uses XOR 6

Use NAND to Implement XOR ã In case there’s no XOR, for example 7

Design Hierarchy 8

Components in Design ã RHS shows what must be designed 9

Reuse is Common ã Certainly forced because of availability of components ã Shortens design times ã Now more flexibility with programmable logic l But still reuse from libraries or intellectual property (IP) l Example: buy a PCI design l Open source, see www. opencores. org ã Note the many logic blocks available in Xilinx library 10

Flow of CAD System Generic Gates Replaces Generic Gates with ones available in Technology Library Netlist is description of connections 11

Technology Mapping ã Full custom l Pixel-Planes chips (machines in lobby) l Memories, CPUs, etc ã Standard cell l Library of cells l Engineer determined interconnection ã Gate arrays l Small circuits with interconnect 12

Hierarchy Example – 4 -bit Equality ã Input: 2 vectors A(3: 0) and B(3: 0) ã Output: One bit, E, which is 1 if A and B are bitwise equal, 0 otherwise 13

Design ã Hierarchical design seems a good approach ã One module/bit ã Final module for E 14

Design for MX module ã Logic function is l It is actually “not Equal” l Can implement as 15

Design for ME module ã Final E is 1 only if all intermediate values are 0 ã So ã And a design is 16

Hierarchical Verilog ã We already saw example of used AND and OR gates instantiation when we ã Just use module name and an identifier for the particular instance 17

Vector of Wires (Bus) ã Denotes a set of wires input [1: 0] S; ã Syntax is [a : b] where a is high-order l So this could be “[0: 1] S” l Order will matter when we make assignments with values bigger than one bit l Or when we connect sets of wires ã NOTE: THIS IS NOT AN ARRAY! 18

MX module mx(A, B, E); input A, B; output E; assign E = (~A & B) | (A & ~B); endmodule 19

ME module me(E, Ei); input [3: 0] Ei; output E; assign E = ~(Ei[0] | Ei[1] | Ei[2] | Ei[3]); endmodule 20

Top Level module top(A, B, E); input [3: 0] A; input [3: 0] B; output E; wire [3: 0] Ei; mx mx m 0(A[0], m 1(A[1], m 2(A[2], m 3(A[3], B[0], B[1], B[2], B[3], Ei[0]); Ei[1]); Ei[2]); Ei[3]); me me 0(E, Ei); endmodule 21

Integrated Circuit ã Known as IC or chip ã Silicon containing circuit l Later in semester we’ll examine design and construction ã Packaged in ceramic or plastic l From 4 -6 pins to hundreds ã Pins wired to pads on chip 22

Bonding 23

Levels of Integration ã SSI l Individual gates ã MSI l Things like counters, single-block adders, etc. l Like stuff we’ll be doing next ã LSI ã VLSI l Larger circuits, like the FPGA, Pentium, etc. 24

Logic Families ã RTL, DTL earliest ã TTL was used 70 s, 80 s l Still available and used occasionally l 7400 series logic, refined over generations ã CMOS l Was low speed, low noise l Now fast and is most common ã Bi. CMOS and Ga. As l Speed 25

Catalogs ã Catalog pages describe chips ã Look at http: //focus. ti. com/lit/ds/scas 014 c. pdf ã Specifications l Pinouts l Packages/Dimensions l Electrical characteristics 26

Electrical Characteristics ã Fan in l max number of inputs to a gate ã Fan out l how many standard loads it can drive (load usually 1) ã Voltage l often 1 V, 1. 2 V, 1. 5 V, 1. 8 V, 3. 3 V or 5 V are common ã Noise margin l how much electrical noise it can tolerate ã Power dissipation l how much power chip needs Ø TTL high Ø Some CMOS low (but look at heat sink on a Pentium) ã Propagation delay – already talked about it 27

Change Topics to ã Verilog l First a couple of syntax styles l Help you program more efficiently ã Verilog test programs 28

Constants in Verilog ã Syntax [size][’radix]constant ã Radix can be d, b, h, or o (default d) ã Examples assign Y = 10; // Decimal 10 assign Y = ’b 10; // Binary 10, decimal 2 assign Y = ’h 10; // Hex 10, decimal 16 assign Y = 8’b 0100_0011 // Underline ignored ã Binary values can be 0, 1 (or x or z) 29

Conditional Assignment ã Equality test S == 2’b 00 ã Assignment assign Y = (S == 2’b 00)? 1’b 0: 1’b 1; l If true, assign 0 to Y l If false, assign 1 to Y 30

4 -to-1 Mux Truth Table-ish module mux_4_to_1_dataflow(S, D, Y); input [1: 0] S; input [3: 0] D; output Y; assign Y = (S (S endmodule == == 2'b 00) 2'b 01) 2'b 10) 2'b 11) ? ? D[0] D[1] D[2] D[3] : : 1'bx ; 31

Verilog for Decision Tree module mux_4_to_1_binary_decision(S, D, Y); input [1: 0] S; input [3: 0] D; output Y; assign Y = S[1] ? (S[0] ? D[3] : D[2]) : (S[0] ? D[1] : D[0]) ; endmodule 32

Binary Decisions ã If S[1] == 1, branch one way assign Y = S[1] ? (S[0] ? D[3] : D[2]) l and decide Y = either D[2] or D[3] based on S[0] ã Else : (S[0] ? D[1] : D[0]) ; l decide Y is either D[2] or D[3] based on S[0] ã Notice that conditional test is for ‘ 1’ condition like in C 33

Instance Port Names ã Module modp(output C, input A); ã Ports referenced as modp i_name(con. C, con. A) ã Also as modp i_name(. A(con. A), . C(con. C)); 34

Parameter ã Can set constant l Like #define parameter SIZE = 16; 35

Verilog for Simulation & Synthesis ã Simulation l you describe the circuit in Verilog l simulate it l good for Ø testing whether your conceptual design works before your spend \$\$ getting it fabricated in silicon ã Synthesis l you describe the behavior in Verilog l use a compiler to “compile” it into a circuit l good for Ø describing large-scale complex systems without every manually building them Ø the “compiler” translates it into a circuit for you! 36

Verilog for Simulation & Synthesis ã Remember: l for simulation: Verilog provides many more language constructs and features l for synthesis: Verilog supports only a subset of the language that makes sense! Ø called “synthesizable subset” 37

ISE ã Make Verilog Test Fixture ã Will create a wrapper (a module) l Instantiating your circuit l It’ll be called UUT (unit under test) ã You then add your test code ã Example on next slides (also Lab 1) 38

Module and Instance UUT module syn_adder_for_example_v_tf(); // DATE: 21: 22: 20 01/25/2004 //. . . Bunch of comments. . . // Instantiate the UUT syn_adder uut (. B(B), . A(A), . C 0(C 0), . S(S), . C 4(C 4) ); . . . endmodule 39

Reg ã It will create storage for the inputs to the UUT // Inputs reg [3: 0] B; reg [3: 0] A; reg C 0; ã The keyword reg means “register” l We’ll talk more about reg next week 40

Wires for Outputs ã That specify bus sizes // Outputs wire [3: 0] S; wire C 4; 41

Begin/End ã Verilog uses begin and end for block ã instead of curly braces 42

Initial ã Initial statement runs when simulation begins initial begin B = 0; A = 0; C 0 = 0; end 43

Procedural assignment ã Why no “assign”? l Because it is not a continuous assignment l It is a one-off assignment! ã Explain more next week when we look at storage/clocking 44

Initialize in Default Test File ã The test file can specify the initial values of inputs to your circuit // Initialize Inputs initial begin B = 0; A = 0; C 0 = 0; end 45

What to Add? ã Need to make simulation time pass ã Use # command for skipping time l time increases by 5 units when you encounter #5 ã Example (note no semicolon after #50) initial begin B = 0; #10; #50 B = 1; end 46

For ã Can use for loop in initial statement block initial begin for(i=0; i < 5; i = i + 1) begin #50 B = i; end 47

Integers ã Can declare for loop control variables l Will not synthesize, as far as I know integer i; integer j; ã Can copy to input regs l There may be problems with negative values 48

There also ã While ã Repeat ã Forever 49

Timescale ã Need to tell simulator what time scale to use ã Place at top of test fixture `timescale 1 ns/10 ps l the first number (1 ns) is the unit for time l the second number (10 ps) is the precision at which time is maintained (e. g. , 5. 01 ns) 50

System Tasks ã Tasks for the simulator ã \$stop – end the simulation ã \$display – like C printf ã \$monitor – prints automatically when arguments change (example next) ã \$time – Provides value of simulated time 51

Monitor // set up monitoring initial begin \$monitor(“At time %d: A=%b , B=%bn", \$time, A, B); end // These statements conduct the actual test initial begin Code. . . end 52

Next Class ã Combinational blocks l multiplexers, decoders, encoders 53