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Combinatorial Logic Circuits Chapter 3 Design Hierarchy reduces the complexity required to represent the schematic diagram of a circuit Combinatorial Logic Circuit Diagrams N Inputs M Outputs Combinatorial Circuit -Programmable Implementation Devices

Combinatorial Logic Circuits Chapter 3 • The purpose of this chapter is to use the knowledge acquired in the previous chapters to formulate systematic design procedures for combinatorial circuits. • The design steps will be related to the use of computer aided design tools. • In this chapter we introduce the use of a hierarchy and top down design, which are essential for the design of digital circuits. • Computer Aided-Design is discussed including Hardware Description Languages (HDL’s) and Logic Synthesis. • Topics related to digital circuit implementation are discussed: –Fan-in –Fan-out –Propagation delays • Design procedures are presented: –Specification –Formulation –Optimization –Fixed implementation & technology mapping –Verification

Combinatorial Logic Circuits Chapter 3 A Combinatorial circuit performs an operation that can be specified by a set of Boolean equations. A Sequential circuit employ elements that store bit values. The outputs of a sequential circuit depend not only on the current input values, but also on past inputs. A combinatorial circuit consists of input variables, output variables, logic gates and interconnections. Each input and output variable consists of a binary signal that takes on values 0 and 1. For n inputs there are 2 n possible binary input combinations N Inputs M Outputs Combinatorial Circuit For each binary combination of the input variables there is one possible binary value on each output specified by a truth table. A combinatorial function can also be described by m Boolean functions, one for each output variable.

Combinatorial Logic Circuits Chapter 3 Design Hierarchy: • A circuit may be specified by a symbol showing its inputs and outputs and a description on how it operates. • A complex digital system may contain millions of interconnected gates. A Very Large Scale Integrated (VLSI) processor often contains tens of millions of gates. • In order to deal with such circuit complexity, a divide and conquer approach is used. A circuit is broken into blocks that are interconnected to form the circuit. The functions of blocks and their interfaces are clearly defined so the circuit obeys the circuit specification. A hierarchy gives a simplified representation of a complex circuit Circuit as 3 input odd function blocks Xo Ao X 1 A 1 X 2 X 3 3 -Input B 0 odd A 2 function Ao X 5 3 -Input A 1 odd B 0 function A 2 X 6 Xo X 1 X 2 Ao 3 -Input B 0 odd A 2 function Ao X 4 X 7 X 8 Symbol for circuit A 1 Zo X 3 X 4 X 5 9 input Zo Odd function X 6 3 -Input A 1 odd B 0 function A 2 X 7 X 8 Each EOR can be represented by 4 NAND Gates Ao A 1 A 2 Circuit using exclusive Or’s Bo

Combinatorial Logic Circuits Chapter 3 The Hierarchy ends in a set of leaves. In this case the leaves consist of NAND gates, referred as primitive blocks. We are only interested in designing the logic. Their function can be defined by a program or description that can serve as a model. 9 -Input Odd function 3 -Input Odd function XOR NAND Gates XOR 3 -Input Odd function XOR

Combinatorial Logic Circuits Chapter 3 We can simplify it even further, where there is only one copy of each block, since the designer can design one three input odd function block and one exclusive-OR block and can use these multiple times respectively. The appearance of a block within a design is called an instance of the block and its use is called instantiation. The block is reusable and this greatly reduces the design effort required for complex circuits. 9 -Input Odd function 3 -Input Odd function XOR

Combinatorial Logic Circuits Chapter 3 • In later chapters we focus on predefined reusable blocks. These blocks provide basic functions used in digital design. • This allows designers to do much of the design process above the primitive block level. • These blocks are in computer aided design tool libraries Top Down Design: The circuit function is specified by text or a Hardware Description Language (HDL) plus constraints on cost, performance and reliability. In automated synthesis, the HDL description is converted to logic automatically. (Ideal approach). In reality its often necessary to perform portions of the design bottom up to make maximum use of predefined modules. A particular circuit design may violate one of the constraints of the initial specification. In this case its often necessary to backtrack upward to a level at which the violation is reached.

Combinatorial Logic Circuits Chapter 3 Computer Aided Design (CAD) Designing complex systems would not be feasible without CAD tools. Libraries of graphics symbols and functional blocks are provided. The primitive and functional blocks have associated models that allow the behavior and the timing of the hierarchical blocks to be verified.

Combinatorial Logic Circuits Chapter 3 Gate Properties: An Integrated Circuit (IC) is a silicon semiconductor crystal, called a chip, containing the gates and storage elements. The chip is mounted on a ceramic or plastic container and the connections are made to the external pins. The number of pins range from 14 to several hundred on large IC’s. Each IC has a numeric designation printed on the package. Vendors publish data sheets or catalogs that describe the functional characteristics of the IC’s. Definitions: The number of gates present on a chip ranges from small scale integrated to Very Large Scale. Small scale Integrated (SSI): Contain several primitive gates usually less that 10. Medium Scale Integrated (MSI): Contain 10 -100 gates: Example simple 4 -bit adder: Large Scale Integrated (LSI): Contain between a 100 and several thousand gates. Example is a simple processor. Very Large Scale Integrated (VLSI): Contains several thousand to tens of millions of gates. Example is a complex microprocessor. Complementary Metal Oxide Semiconductor (CMOS): Used for high circuit density, high performance low power applications. Gallium Arsenide (Ga. As) and Silicon Germanium(Si. Ge) are used for very high speed circuits.

Combinatorial Logic Circuits Chapter 3 Technology Parameters: Parameters used to characterize an implementation technology: Fan-in: specifies the number of inputs available on a gate. Usually restricted to 4 or 5. (related to gate speed) Fan-out: specifies the number of standard loads driven by a gate output. Maximum fan-out, specifies the fan-out that the output can drive without impairing gate performance. Noise margin: is the maximum external noise voltage superimposed on a normal input value that will not cause an undesirable change in the circuit output. Propagation Delay: Is the time required for a change in value of a signal to propagate from input to output. In In Out Tphl Tplh The high to low propagation Tphl is the delay measured from the reference voltage IN to the reference voltage OUT Tpd is the propagation delay = max(Tphl, Tplh) Reason for this is to find the longest time for a signal to propagate from inputs to outputs Power Dissipation: Is the power drawn from the power supply and consumed by the gate. The power consumed is dissipated as heat. Related to the operating temperature and cooling requirements of the chip.

Combinatorial Logic Circuits Chapter 3 Takes ~1 NS to go from Logical 0 to 1 A B No delay Transport Delay Time (Ns) 0 1 2 3 4 5 6 7 8 AND Gate Example of Transport and Inertial Delays

Combinatorial Logic Circuits Chapter 3 Fan-out: Each input on a given gate provides a load on the output of the driving gate which is measured in standard load units. The input to a specific inverter can have a standard load of 1. 0. If a gate drives six inverters then it would be 6. 0. The output of a gate has a maximum load it can drive called maximum fan-out. The load on the output of a gate determines the time required for the output of the gate to change fro H to L and L to H. If the load on the output is increased then this time transition time is increases. The propagation delay is also increased. Ex: Calculation of gate delay based on fan-out. A 4 input NAND gate output is attached to the inputs of the following gates. -4 input NOR gate 0. 8 standard load -3 input NAND gate 1. 0 standard load -Inverter 1. 0 standard load The formula for the delay of the 4 input NAND gate is (CMOS gates) Tpd=0. 07 + 0. 021 X SL ns (where SL is the sum of the standard loads driven by the gate) (ignoring the wiring delay) (Tpd is the propagation delay) Tpd=0. 07 + 0. 021 x (0. 8 + 1. 0) = 0. 129 ns

Combinatorial Logic Circuits Chapter 3 Cost: The cost is based on the area occupied by the layout cell for the circuit. The layout cell area is proportional to the size of the transistors and the wiring in the gate layout. Ignoring the wiring area, the area of the gate is proportional to the number of transistors in the gate, which is usually proportional to the gate input count. Positive and Negative Logic: Data sheet for CMOS gate where Choosing the High level to represent logic 1 defines a positive-logic system. Choosing the Low level to represent logic 1 defines a negative logic system. H=5. 0 Volts L= 0. 0 Volts X Y Z L L H X Y CMOS Gate H H Truth Table Gate block diagram Z

Combinatorial Logic Circuits Chapter 3 X 0 0 0 1 1 1 X Y Z 0 Negative Logic Z 0 Positive Logic Y 0 1 1 X 1 0 1 Y 1 1 0 X Y Z Z The small triangles on the inputs and outputs are polarity indicators , which signifies that negative logic is assumed for the corresponding signal (also called taking the dual of the gate function. We will use positive logic in the text.

Combinatorial Logic Circuits Chapter 3 Design Procedure: The design of a combinatorial circuit starts from the specification of the problem and culminates in a logic diagram (or netlist that describes a logic diagram) The procedure involves the following steps: 1) Specification: Write a specification for the circuit 2) Formulation: Derive the truth table or initial Boolean equations that define the required relationships between inputs and outputs. 3) Optimization: Apply two-level and multi-level optimization. Draw a logic diagram or netlist for the resulting circuit using AND , OR’s and Inverters. 4) Technology Mapping: Transform the logic diagram or netlist to a new diagram or netlist using available implementation Technology Mapping replaces AND, OR Gates and Inverters with gates from the technology library 5) Verification: Verify the correctness of the final design. Netlist: When using a HDL (Hardware description Language, Xi. Linx) a structural description describes the interconnection of components. This structural description is referred to as a netlist, used as input to a logic simulator.

Combinatorial Logic Circuits Chapter 3 Example (Design Procedure: ) Design of a BCD to Excess-3 Code converter: (Add 3 to every BCD digit) Step 1) Specification: The Excess-3 code for a decimal digit is the binary combination corresponding to the decimal digit plus 3. An example is given the decimal digit 5 the binary combination is 5+3=8 (1000). • Each BCD digit is four bits labeled A, B, C, D. • Each Excess-3 digit is four bits labeled W, X, Y, Z. Step 2) Formulation: The Excess-3 code is obtained by adding 0011 (3) to each BCD codes 1010 through 1111 are not listed and can be treated ad don’t care conditions. Decimal Output Excess-3 A B C D W X Y Z 0 0 0 0 1 1 1 0 0 0 1 0 0 2 Truth Table: Input BCD 0 0 1 0 1 3 0 0 1 1 0 4 0 1 0 0 0 1 1 1 5 0 1 1 0 0 0 6 0 1 1 0 0 1 7 0 1 1 0 1 0 8 1 0 0 0 1 1 9 1 0 0 1 1 1 0 0 A K-Map will be generated for each output variable K-Map for Y K-Map for X K-Map for W K-Map for Z

Combinatorial Logic Circuits Chapter 3 Step 3: Optimization: This is a four variable function and we use the Karnaugh maps for optimization. • For each output variable W, X, Y, Z we need a separate K-Map. Truth Table for W=1 5 6 7 8 9 A 0 0 0 1 1 B 1 1 1 0 0 C 0 1 1 0 0 D 1=ABCD 0=ABCD 1=ABCD BC CD BD A AB 00 01 11 1 ABCD ABCD 1 1 X X ABCD 00 01 11 10 X X X W=A + BC + BD 10 X Don’t-Care BCD numbers 10 -15 1010, 1011, 1100, 1101, 1110, 1111 Optional to use these elements

Combinatorial Logic Circuits Chapter 3 Step 3: Optimization: This is a four variable function and we use the Karnaugh maps for optimization. • For each output variable W, X, Y, Z we need a separate K-Map. Truth Table for X=1 1 2 3 4 9 BD B 0 0 0 1 0 C 0 1 1 0 0 D 1=ABCD 0=ABCD 1=ABCD BC CD AB 00 BCD A 0 0 1 01 11 00 01 11 1 ABCD X X ABCD ABCD 1 10 ABCD X=BC + BD + BCD

Combinatorial Logic Circuits Chapter 3 ABCD Step 3: Optimization: This is a four variable function and we use the Karnaugh maps for optimization. • For each output variable W, X, Y, Z we need a separate K-Map. Truth Table for Y=1 1 3 4 7 8 A 0 0 1 B 0 0 1 1 0 C 0 1 0 D 0=ABCD 1=ABCD 0=ABCD CD AB 00 CD 01 11 10 00 01 11 1 10 1 ABCD 1 1 ABCD X X ABCD 1 X X ABCD Y=CD + CD CD

Combinatorial Logic Circuits Chapter 3 Step 3: Optimization: This is a four variable function and we use the Karnaugh maps for optimization. • For each output variable W, X, Y, Z we need a separate K-Map. Truth Table for Z=1 0 2 4 6 8 A 0 0 1 B 0 0 1 1 0 C 0 1 0 D 0=ABCD 0=ABCD CD AB 00 01 11 10 00 D 1 1 ABCD 01 ABCD 11 10 1 1 ABCD X X X ABCD 1 X X ABCD Z=D X

Combinatorial Logic Circuits Chapter 3 Optimization (cont): Each of the four maps represents one of the outputs of the circuit. W=A + BC + BD X=BC + BD + BCD Y=CD + CD Z=D A W B X C D Y Z

Combinatorial Logic Circuits Chapter 3 Technology Mapping: Starting with an optimized circuit we develop a new circuit using common gate elements. NAND gates are often used, since we can represent other gates using them. As shown from Chapter 2: A gate type that alone can be used to implement all Boolean functions is called a Universal gate. Using a NAND gate as a AND gate X XY Y Using a NAND gate as a OR gate X X X+Y Y NAND Gate X Y F X F=X Y Y Z= XY Y X + Y 0 0 1 1 0 0 0 1 0 1 1 0 0 1 1 0 2 1 1 0 0 1

Combinatorial Logic Circuits Chapter 3 Cell Library for technology mapping: ( to NAND Logic) Cell Name Cell Schematic Normalized Typical Area Inverter 1. 0 Typical Input to Basic Function Input Load Output Delay 1. 00 Template 0. 04 +. 012 * SL (referred to as 1. 0 Standard Load) 2 NAND 1. 25 1. 00 . 05 +. 014 * SL Basic building block 2 NAND 3 NAND 1. 50 1. 00 0. 06 +. 017 * SL Procedures (Replace AND-OR gates with equivalent circuits) AND OR

Combinatorial Logic Circuits Chapter 3 Using Technology Mapping BCD to Excess-3 Code Converter A W B X C D Y (AOI) And –or-Inverter Z

Combinatorial Logic Circuits Chapter 3 5) Verification / Simulation: The goal is to determine whether a given circuit implements its specified function (Boolean equations and HDL are used) Original Specification Technology Mapped Circuit Result (should be same as Specification) Dec Input BCD Output Excess-3 A B C D W X Y Z 0 0 0 0 1 1 1 0 0 0 1 0 0 2 0 0 1 0 1 3 0 0 1 1 0 4 0 1 0 0 0 1 1 1 5 0 1 1 0 0 0 6 0 1 1 0 0 1 7 0 1 1 0 1 0 8 1 0 0 0 1 1 9 1 0 0 1 1 1 0 0 A W B X C D Y (AOI) And –or-Inverter Z

Combinatorial Logic Circuits Chapter 3