CDF Run II Silicon Tracking Projects 8 th

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CDF Run II Silicon Tracking Projects 8 th INTERNATIONAL WORKSHOP ON VERTEX DETECTORS Texel, CDF Run II Silicon Tracking Projects 8 th INTERNATIONAL WORKSHOP ON VERTEX DETECTORS Texel, Netherlands 20 -25 JUNE 1999 Presented by Alan Sill Department of Physics Texas Tech University Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 1

Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 2

Goals for CDF Run II Silicon l Increase acceptance and coverage of luminous region Goals for CDF Run II Silicon l Increase acceptance and coverage of luminous region along beam ä Previous CDF vertex detectors covered interactions within |z| < 0. 27 m, New silicon detectors designed to cover |z| < 0. 43 m ä Interaction region expected to be more concentrated in z in Run II ä Increase silicon angular acceptance to cover approximately 2. ä Overall effect should be approximately a factor of 2 increase in acceptance for particles with good tracking and vertexing l Improve top tagging for high-p. T physics: l Improve B physics capability of the experiment Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 3

CDF II Detector - Run II Configuration Alan Sill, Texas Tech University CDF Run CDF II Detector - Run II Configuration Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 4

Quadrant of CDF II Tracker LAYER 00 Alan Sill, Texas Tech University CDF Run Quadrant of CDF II Tracker LAYER 00 Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 5

Fermilab Run II Silicon Alan Sill, Texas Tech University CDF Run II Silicon Vertex Fermilab Run II Silicon Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 6

CDFII Silicon Tracker: Layer 00 + SVXII + ISL Goals and Features: l Precise CDFII Silicon Tracker: Layer 00 + SVXII + ISL Goals and Features: l Precise 3 D track impact parameters ä B tagging: top, SUSY, Higgs ä B Physics l Improved forward coverage ä 0 2 l Level II displaced-track trigger (SVT) ä Hadronic B decays ä Calibration triggers l l Alan Sill, Texas Tech University CDF Run II Silicon Improved p. T resolution High tracking efficiency with good purity Vertex ‘ 99, 6/21 -25/1999 p. 7

SVX 3 D R/O Chip • Rad-hard 0. 8 um Honeywell CMOS • Dynamic SVX 3 D R/O Chip • Rad-hard 0. 8 um Honeywell CMOS • Dynamic pedestal subtraction • Tested to ~ 4 MRad • Common to all Run II CDF silicon projects • Deadtimeless Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 8

SVX 3 D R/O Chip Alan Sill, Texas Tech University CDF Run II Silicon SVX 3 D R/O Chip Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 9

* Readout Chip Specifications Alan Sill, Texas Tech University CDF Run II Silicon Vertex * Readout Chip Specifications Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 10

SVX II Collaboration Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ SVX II Collaboration Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 11

SVX II: 3 Barrels, 5 Layers Alan Sill, Texas Tech University CDF Run II SVX II: 3 Barrels, 5 Layers Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 12

SVX II vs. Previous Detector Alan Sill, Texas Tech University CDF Run II Silicon SVX II vs. Previous Detector Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 13

SVXII Parameters Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, SVXII Parameters Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 14

* Silicon Specifications SVX II silicon sensor specifications for Hamamatsu (90 o layers 0, * Silicon Specifications SVX II silicon sensor specifications for Hamamatsu (90 o layers 0, 1, 3) and Micron (1. 2 o layers 2, 4) Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 15

SVXII Barrel Fabrication Fixture for installing SVX II ladders into barrel (precision aligned bulkhead SVXII Barrel Fabrication Fixture for installing SVX II ladders into barrel (precision aligned bulkhead pair) Test assembly with mock aluminum bulkheads and mechanically accurate ladders Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 16

SVX II Ladders SVX II half ladder, consisting of two silicon sensors wirebonded with SVX II Ladders SVX II half ladder, consisting of two silicon sensors wirebonded with the readout electronics mounted on the first sensor. Wirebonds HDI cable Rohacell/Carbon Support Si Sensors Bridge Connection Electrical Component Hybrid SVX 3 Chips Wirebonds Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 17

Layer 00 Collaboration FNAL, INFN-Pisa, INFN-Padova, LBNL, Purdue, U. California-Davis, U. Florida, U. Glasgow, Layer 00 Collaboration FNAL, INFN-Pisa, INFN-Padova, LBNL, Purdue, U. California-Davis, U. Florida, U. Glasgow, U. Liverpool Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 18

Layer 00 Resolution improvements: l Beam pipe layer of 1 -Sided Silicon ä Improve Layer 00 Resolution improvements: l Beam pipe layer of 1 -Sided Silicon ä Improve IP resolution - Better B tagging for higgs, SUSY ä Extend useful lifetime ä Long-term operational experience with LHC rad-hard silicon Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 19

Layer 00 Design Values Alan Sill, Texas Tech University CDF Run II Silicon Vertex Layer 00 Design Values Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 20

Layer 00 in SVX II 2. 2 cm Alan Sill, Texas Tech University CDF Layer 00 in SVX II 2. 2 cm Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 21

ISL Collaboration FNAL, INFN-Pisa, INFN-Padova, INFN-Bologna, LBNL, Texas A&M, U. California-Davis, U. California-Los Angeles, ISL Collaboration FNAL, INFN-Pisa, INFN-Padova, INFN-Bologna, LBNL, Texas A&M, U. California-Davis, U. California-Los Angeles, U. Cassino, U. Florida, U. Karlsruhe, U. Rochester, U. Tsukuba, Osaka City University Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 22

Intermediate Si Layers CDF ISL ä CDF ISL: Proposal and Conceptual Design (FNAL). Final Intermediate Si Layers CDF ISL ä CDF ISL: Proposal and Conceptual Design (FNAL). Final Design (Pisa). - Emphasis on simplicity and low cost. ä Space frame manufactured in Italy; INFN Pisa & FNAL are the main production sites (roughly half each). Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 23

ISL Modules l Overview of Design ä C Fiber substrate - All bond pads ISL Modules l Overview of Design ä C Fiber substrate - All bond pads are accessible from both sides ä 3 Sensors - 112 mm pitch (both sides) Double Sided 1. 2 o Stereo Angle ä Hybrid mounted off Silicon - l 8 readout chips per hybrid Module Production ä Mechanical Fabrication: - less than 2 hours ä Wirebonding: - 20 minutes per side (roughly 1 hour total w/setup) ä Testing & Repair - Under study Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 24

ISL Ladder Assembly l Pilot production ladders ä Karslruhe fixtures refined w/use l Hybrids ISL Ladder Assembly l Pilot production ladders ä Karslruhe fixtures refined w/use l Hybrids ä Expect all substrates end of summer ä Prototypes operate as expected ä Final assembly limited by SVX 3 D availability Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 25

CDF Run II DAQ l l l Fully pipelined DAQ+Trigger architecture (396 -->132 ns) CDF Run II DAQ l l l Fully pipelined DAQ+Trigger architecture (396 -->132 ns) Operates “deadtimeless” One of our largest subprojects Total board count >15, 000. ~100 different custom boards ä ~ 35 High volume boards (qty >100) l l Alan Sill, Texas Tech University CDF Run II Silicon For SVX 3 D, everything up to L 1 accept is on the chip SVT (not covered here) provides L 2 displaced-track trigger Vertex ‘ 99, 6/21 -25/1999 p. 26

* Silicon DAQ Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ * Silicon DAQ Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 27

SVXII DAQ Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, SVXII DAQ Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 28

* ISL DAQ each HDI (and DOIM) has 16 chips — 4 per side * ISL DAQ each HDI (and DOIM) has 16 chips — 4 per side on each of two ladder ends Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 29

Final Assembly / Installation Alan Sill, Texas Tech University CDF Run II Silicon Vertex Final Assembly / Installation Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 30

Simulation: Run II CDF Si ROOT based Open Inventor based Alan Sill, Texas Tech Simulation: Run II CDF Si ROOT based Open Inventor based Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 31

Expected Performance • Reported previously for SVX II, ISL • Improvements with L 00: Expected Performance • Reported previously for SVX II, ISL • Improvements with L 00: Good overall top tagging Improved IP resolution Alan Sill, Texas Tech University CDF Run II Silicon More tracks In top b tag Should survive ~10 MRad Vertex ‘ 99, 6/21 -25/1999 p. 32

Conclusions l SVXII + ISL + L 00 design provides complete silicon tracker that Conclusions l SVXII + ISL + L 00 design provides complete silicon tracker that should give robust performance throughout Run II Silicon on track for complete delivery by early to mid 2000 Hybrid substrates complete (SVXII) or will be soon (ISL, L 00); population in progress SVX 3 D chip provides rad-hard deadtimeless operation l PROBLEMS: l l l ä Slow delivery of some silicon has delayed sensor production ä Yield problems and other difficulties with Honeywell SVX 3 D ä Infancy failures of some chips l SUCCESSES: ä Overall the projects are on track ä Many problems solved ä Installation sometime in 2000 should be possible Alan Sill, Texas Tech University CDF Run II Silicon Vertex ‘ 99, 6/21 -25/1999 p. 33




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