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2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab at FEUP-DEEC Grasping 2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab at FEUP-DEEC Grasping the Potencial of Digital Signal Laboratory Processing through Real-Time DSP Laboratory Experiments Aníbal J. S. Ferreira*^, Francisco J. O. Restivo* * Faculdade de Engenharia da Universidade do Porto Departamento de Engenharia Electrotécnica e Computadores Rua Dr. Roberto Frias, 4200 -465 Porto, Portugal ^ INESC Porto, Portugal [email protected] pt, [email protected] up. pt AJF/FJR 1

2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab at FEUP-DEEC Abstract 2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab at FEUP-DEEC Abstract • A new DSP laboratory course has been included in the Electrical and Computer Engineering curriculum at the Faculdade de Engenharia da Universidade do Porto, in Portugal, since the school year of 1999/2000. This paper addresses the context and motivation underlying this new course, outlines its structure and methodology, highlights the design and goals of all DSP experiments currently proposed for the 13 weeks of the semester, and reports on the receptivity students have expressed to this elective course. The course is based on the TI C 31 Starter Kit and tries to combine full use of its resources with a representative diversity of efficient digital signal processing techniques and associated application scenarios. A perspective is also given on current plans to reinforce DSP expertise at the graduate level. AJF/FJR 2

Summary • EEC at FEUP-DEEC – basic structure and topics basic to DSP – Summary • EEC at FEUP-DEEC – basic structure and topics basic to DSP – EEC 4162 (PDS) 2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab at FEUP-DEEC • EEC 5274 (PDSTR) – – focus, rational, history C 31 starter kit course structure and organization DSP laboratory experiments – students feed-back • Looking Forward – new challenges • Conclusion AJF/FJR 3

EEC at FEUP-DEEC • basic structure – 1 st and 2 nd year core EEC at FEUP-DEEC • basic structure – 1 st and 2 nd year core – 3 rd year students select a branch • APEL: industrial automation, production and electronic systems • E: energy systems • TEC: telecommunication, electronic and computer systems 2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab at FEUP-DEEC – 4 th and 5 th year: mandatory + elective disciplines per branch 3 rd Year APEL 1 st Year AJF/FJR 2 nd Year 4 th Year APEL 5 th Year APEL 3 rd Year E 4 th Year E 5 th Year E 3 rd Year TEC 4 th Year TEC PDSTR 5 th Year TEC 4

EEC at FEUP-DEEC 2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab EEC at FEUP-DEEC 2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab at FEUP-DEEC • basics to DSP during the first 3 years: – – – – programming Fourier transform / Fourier analysis Laplace transform Z transform sampling / modulation filtering random processes noise • other topics: • • AJF/FJR digital systems signal theory circuit theory systems theory • • algorithms and data structures microprocessors probability and statistics telecommunications 5

EEC 4162 (PDS) • syllabus 2 nd IEEE SPE, October 13 -16, GA, 2002 EEC 4162 (PDS) • syllabus 2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab at FEUP-DEEC – – 3 -hour class / week : theory + illustrative problems 2 -hour class / week : problems, application of theory, 6 individual work assignments / semester (e. g. , using Matlab) main topics: • • • AJF/FJR discrete signals and systems sampling and reconstruction of analogue signals linear-time invariant systems structures for the realization of LTI systems FIR and IIR filter design finite word length effects decimation and interpolation the discrete Fourier transform overlap-add and overlap-save methods of FFFD response of LTI systems to random discrete signals FFT and its implementation 6

EEC 4162 (PDS) • teaching experience reveals that 2 nd IEEE SPE, October 13 EEC 4162 (PDS) • teaching experience reveals that 2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab at FEUP-DEEC – typically, a pencil and paper approach, even if complemented with simulation exercises using Matlab, is not enough for the student to grasp the advantage and potential of digital signal processing in many application areas including multimedia, telecommunications, control, and consumer electronics – as a consequence, a hands-on DSP laboratory course has been included, since 1999, in the EEC curriculum, so as to motivate students to explore DSP based solutions to practical problems such as filtering, Fourier analysis or Single Side Band Modulation (SSB) AJF/FJR 7

EEC 5274 (PDSTR) • profile 2 nd IEEE SPE, October 13 -16, GA, 2002 EEC 5274 (PDSTR) • profile 2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab at FEUP-DEEC – – elective course based on DSP laboratory experiments offered during the 8 th semester of the EEC curriculum part of the EEC curriculum since 1999 student preference • 1999/2000: 16 students • 2000/2001: 32 students • 2001/2002: 22 students – focus • practical digital signal processing issues and applications • efficient realization structures • real-time processing constraints – approach • advantages of DSP are demonstrated by lab examples covering a representative diversity of application scenarios • student is challenged with specific DSP design and realization issues. AJF/FJR 8

EEC 5274 (PDSTR) • selected DSP laboratory platform: C 31 starter Kit – DSP EEC 5274 (PDSTR) • selected DSP laboratory platform: C 31 starter Kit – DSP initialization kit able to realize many different laboratory experiments running in real-time 2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab at FEUP-DEEC – includes assembler and (windows-based) debugger environment (Go-DSP Code Explorer) – availability of many demonstration code examples and support (C 31 teaching kit), and literature – kind support of the Texas Instruments European University Programme AJF/FJR 9

EEC 5274 (PDSTR) • modus operandi – 1. 5 hour class / week • EEC 5274 (PDSTR) • modus operandi – 1. 5 hour class / week • theory, demonstration of concepts 2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab at FEUP-DEEC – 2. 5 hour class / week • laboratory work: design, realization and performance assessment of algorithms running in real-time – students are encouraged to keep the kit between classes • eases preparation for the lab work • opportunity for students to explore beyond the strict realization goals of each lab work • self-learning AJF/FJR 10

EEC 5274 (PDSTR) • theory and laboratory classes – first part (theory) • use EEC 5274 (PDSTR) • theory and laboratory classes – first part (theory) • use of the development environment of the C 31: assembler, debugger, C 31 architecture, peripherals and instruction set 2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab at FEUP-DEEC – second part (theory) • real-time realization of algorithms for FIR; IIR and FIR-adaptive filtering, multirate processing using polyphase decomposition, FFT and spectral analysis, SSB modulation (Hilbert Transform) – laboratory classes • 10 lab experiments and reports during the 13 -week semester • each report: main results and conclusions of each lab work • early feed-back is given to students report (corrected and graded) of previous week is returned to students Week AJF/FJR goals for week n+1 revealed on web site n students hand-over short report at end of each lab class 11

EEC 5274 (PDSTR) • syllabus – presumes the core knowledge of the pre-requisite DSP EEC 5274 (PDSTR) • syllabus – presumes the core knowledge of the pre-requisite DSP course (EEC 4162), including efficient realization structures and FFT 2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab at FEUP-DEEC – new topics: • filter banks, uniform filter banks and their relation to the DFT • half-band filters, M-band filters, power complementary filters • the QMF filter bank, design and implementation issues, multiresolution analysis using the QMF • adaptive filtering • polyphase decomposition of interpolation and decimation filters and their efficient realization • Hilbert Transformer and SSD modulation AJF/FJR 12

EEC 5274 (PDSTR) • laboratory experiments 2 nd IEEE SPE, October 13 -16, GA, EEC 5274 (PDSTR) • laboratory experiments 2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab at FEUP-DEEC caracterization of the problem DSP conceptual approach validation in Matlab identification of opportunities for efficient realization assembly code debugging performance assessment AJF/FJR 13

EEC 5274 (PDSTR) - Lab experiments • 1. verification of the aliasing in sampling EEC 5274 (PDSTR) - Lab experiments • 1. verification of the aliasing in sampling 2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab at FEUP-DEEC – goal: estimate the sampling frequency just by hearing the result at the output of the system, due to a sinusoid of varying (and known) frequency that is injected at the input AAF A/D C 31 D/A AIF ON/OFF AJF/FJR 14

EEC 5274 (PDSTR) - Lab experiments • 2. waveform generation and converter testing 2 EEC 5274 (PDSTR) - Lab experiments • 2. waveform generation and converter testing 2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab at FEUP-DEEC – goal: take advantage of circular addressing in order to synthesize different waveformss, and of the lookp-back mode of AIC in order to evaluate the accumulated quality of the D/A and A/D conversion (delay, noise floor, differential non-linearity) AAF AJF/FJR A/D C 31 D/A AIF 15

EEC 5274 (PDSTR) - Lab experiments • 3. fixed point processing vs. floating point EEC 5274 (PDSTR) - Lab experiments • 3. fixed point processing vs. floating point processing 2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab at FEUP-DEEC – goal: identify issues of fixed representation of numbers (namely the need for scaling) in recursive processing, versus floating-point sin(n ) c 1 sin[(n+1) ] c 2 cos(n ) cos[(n+1) ] c 3 c 4 AJF/FJR 16

EEC 5274 (PDSTR) - Lab experiments • 4. FIR filtering 2 nd IEEE SPE, EEC 5274 (PDSTR) - Lab experiments • 4. FIR filtering 2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab at FEUP-DEEC – goal 1: H(z)=1 -z-15, compare theoretical H(ej ) vs. experimental – goal 2: realization of FIR equiripple h(n), 2 h(n)cos n /2, (-1)nh(n) /2 /2 AJF/FJR /2 17

EEC 5274 (PDSTR) - Lab experiments • 5. IIR filtering – goal 1: 6 EEC 5274 (PDSTR) - Lab experiments • 5. IIR filtering – goal 1: 6 th order IIR, type 2 realization structure – goal 2: compare simulated response vs. experimental response b 0 2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab at FEUP-DEEC x(n) Z -1 a 1 b 1 Z Z a. N-1 AJF/FJR y(n) -1 -1 b. M-1 18

EEC 5274 (PDSTR) - Lab experiments • 6. five vowel synthesizer – goal: synthesize EEC 5274 (PDSTR) - Lab experiments • 6. five vowel synthesizer – goal: synthesize /à/, /é/, /i/, /ó/, /u/ on a DSK using three formants 2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab at FEUP-DEEC • didactic application allows to give each implementation a personal flavor (high motivation impact) • quality improvements by modulating pitch AJF/FJR 19

EEC 5274 (PDSTR) - Lab experiments • 7. interpolation using polyphase filters – goal: EEC 5274 (PDSTR) - Lab experiments • 7. interpolation using polyphase filters – goal: efficient realization of interpolation filter, experimental evaluation of of the sinc function associated to the D/A reconstruction when 4 -fold interpolation is used and when not 2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab at FEUP-DEEC R 0(z) R 1(z) 4 /4 AJF/FJR AAF A/D x(n) R 2(z) R 3(z) C 31 D/A n=3 n=2 n=1 n=0 AIF 20

EEC 5274 (PDSTR) - Lab experiments • 8. adaptive filtering 2 nd IEEE SPE, EEC 5274 (PDSTR) - Lab experiments • 8. adaptive filtering 2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab at FEUP-DEEC – goal 1: realization and assessment of the operation of an adaptive filter (32 tap FIR, LMS) – goal 2: implementation of the configuration insuring real-time echo canceling D/A A/D adaptive filter D/A AJF/FJR g. Z-1 adaptive filter + + A/D what are the differences ? 21

EEC 5274 (PDSTR) - Lab experiments • 9. FFT assembly implementation – goal 1: EEC 5274 (PDSTR) - Lab experiments • 9. FFT assembly implementation – goal 1: assembly implemention of a radix-2 FFT based on a Clike optimized (Matlab) code (N=64) – goal 2: assessment of the implementation when used as a simple real-time spectrum analyser 2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab at FEUP-DEEC x(0) x(4) X(0) W N 0 X(1) -1 x(2) x(6) W N 0 W N 2 -1 X(3) -1 x(1) x(5) W N 0 x(3) W N 0 WN WN 0 W N 2 -1 AJF/FJR WN 0 X(4) -1 W N 1 -1 x(7) X(2) -1 -1 -1 2 W N 3 -1 X(5) X(6) -1 X(7) -1 22

EEC 5274 (PDSTR) - Lab experiments • 10. single side band modulation – goal: EEC 5274 (PDSTR) - Lab experiments • 10. single side band modulation – goal: design and realization of a band-pass filter, Hilbert transformer, SSB modulator based on analytic signal generation 2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab at FEUP-DEEC down-shift up-shift AJF/FJR spectral-inversion 23

EEC 5274 (PDSTR) • students feed-back – plus: • tangible and intuitive linking between EEC 5274 (PDSTR) • students feed-back – plus: • tangible and intuitive linking between theory and practice • methodology elicits insight and promotes application 2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab at FEUP-DEEC – minus • more time to prepare and to “play” • sooner indication of lab work description • lab classes > 2, 5 hours – regarding possibility of additional DSP lab course • 50% say yes if addressing more application scenarios and combining video and audio AJF/FJR 24

Looking Forward • new challenges – new starter kit ? VLIW TMS 320 C Looking Forward • new challenges – new starter kit ? VLIW TMS 320 C 6711 ? 2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab at FEUP-DEEC – new DSP issues • utilization of cache • utilization of DMA • combined C, assembly code optimization AJF/FJR 25

Conclusion • PDSTR: an ECE advanced undergraduate level DSP laboratory course – all course Conclusion • PDSTR: an ECE advanced undergraduate level DSP laboratory course – all course material (in Portuguese) is available on the Web 2 nd IEEE SPE, October 13 -16, GA, 2002 DSP Lab at FEUP-DEEC – hands-on DSP laboratory experience • • consolidates knowledge stimulates criativity helps to develop a rewarding sense of achievement motivates final-year course projects using DSP technology – plans for a new DSP lab (C 6711) at the graduate level • focus on complex and complete algorithm implementation AJF/FJR 26